I did some measurements trying to find the SPI input sampling timing:
Because it is impossible to measure the sampling point directly, I connected SCK through a variable delay line to the SDI pin.
I used the most common SPI mode 0 (CKE=1, CKP=0) on a PIC24FJ16GA002 running at 14.9MHz.
Here you can see the data I got back when reading from SPI:
For SMP=0 it is always missing the first SCK high period, so the sampling point is before the first SCK rising edge.
It sees the end of the first SCK high period when delayed by 58ns (for divider=2) and 125ns (for divider=4). That is around 10ns before the next SCK rising edge in both cases.
So with SMP=0 it is probably sampling at the same time it outputs the SCK rising edge internally.
But what looks strange is the odd duty cycle of the sampled data. The signal going into SDI pin has almost 50% duty cycle like the SCK pin, but the sampled data seems to prefer 0s instead of 1s, especially at higher clock rates.
SMP=1 looks a bit more difficult at first glance:
For SPI clock divider 2 =(7.46MHz = 134ns) the sampling point seems to be 40ns after SCK rising edge (or 27ns before the falling edge).
For SPI clock divider 4 =(3.73MHz = 268ns) the sampling point seems to be 107ns after SCK rising edge (or 27ns before the falling edge).
But when looking at the other end of the data (where 1s turn into 0s), we also get a sampling point of 10ns before falling edge.
So, to get correct data in all cases, it must be stable at least in the 30ns-5ns window before the sampling SCK edge (the necessary setup/hold time probably gets larger when changing to a different operating voltage or temperature).
So the timing diagram shown in the SPI section is correct, but the timing shown in the electrical characteristics section of many (or all?) PIC24/dsPIC33 is wrong, because they show the timing for SMP=0 but say it is for SMP=1.
That means I have some controllers with probably marginal SPI timing in the field, because I have trusted the electrical characteristics section, but they screwed up the specs in every datasheet. Well done Microchip.
There is probably some difference in timing between different microcontrollers because of the peripheral pin select feature used for routing the SPI peripheral to the IO pins, but the basic behaviour is probably identical for most other PIC families using a similar SPI peripheral.
I also tried measuring using SPI clock divider = 1 (14.9MHz is out of specs, only 10MHz are allowed). Here it gets more interesting:
For SMP=0 it confirms the 10ns before rising edge.
For SMP=1 it now also misses the first SCK high period, because the minimum delay of 7.5ns my delay line generates leaves less than 27ns before the falling edge. If I skip the delay line completely, it is just enough so it can sample the high level. That also confirms the previous measurement.
So when using 16MHz SPI clock frequency and SMP=1 the input signal must be stable almost during the full SCK high period. I haven't done any measurements over the full voltage and temperature range, but according to this measurement using 16MHz SPI clock with SMP=1 should be fine. That matches my previous experience with overclocking SPI.