Searching a microcontroller

[blewisjr]

The hardest part is going to be getting the amount of I/O you want.  For instance the Enhanced Mid-Range PIC16F1829 goes up to 32Mhz but only has 17 I/O ports.  The best bang for your Buck will probably be the PIC18F44K22 which can hit 64Mhz as a 8-bit chip C program friendly and has 35 output pins and 36 input pins.  Here is the data sheet for the chip maybe it will suit your needs.

http://ww1.microchip.com/downloads/en/DeviceDoc/41412F.pdf

[lgbeno]

I think a cpld is the perfect solution.  And can emulate the mapper chip exactly.

Check out the max ii micro kit from terasic.  Also just FYI you'll still need the micro for the USB side of things but your life will be so much easier with a cpld for the bus interface.  It's a good learning opportunity too...

[pyroesp]

Does a CPLD have a volatile memory like an FPGA, or does it keep its program if you reset/unpower it ?
Do any of you have like a "cheap" starter kit with a CPLD ?
I don't know anything about it so I'd like to try a CPLD starter kit first.

I think a cpld is the perfect solution.  And can emulate the mapper chip exactly.

Check out the max ii micro kit from terasic.  Also just FYI you'll still need the micro for the USB side of things but your life will be so much easier with a cpld for the bus interface.  It's a good learning opportunity too...

I checked your MAX II Micro Kit, looks great. From terasic they "phased out", whatever that is, I can't order one from there, maybe somewhere else ? Or another kit ?

Yes, if the CPLD is prorgammed like a mapper, I can use the 18F4550 as a USB Flash programmer as that one should have enough I/O.
The idea was to do it with a microcontroller, but as you said, using a CPLD can be a good learning opportunity.
I just hope the programming language isn't as bad as the one I used a couple years ago ...

Anyways, thanks for the replies.

[alm]

I think a CPLD like the XC9500XL series from Xilinx would be a good option (specifically the XC9572XL). These are 3.3V though with 5V tolerant I/O. IIRC there are also 5V versions but these are twice as expensive. I always use the VHDL language to program these but that is because I know VHDL.

There used to be the XC9500, but I'm pretty sure it's discontinued.

[C]

Lock in
back in the Z80 time getting memory to work that fast was a big problem.
A small change in memory speed, could add a complete wait state.
Been there done that. But what is happening is a form of lock in. Read the clock speed, set the clock speed to 4Mhz.
That is missing what you really want, A FAST COMPUTER. Some designers asked the question a different way. How fast can the clock be and use this memory. 3.8 Mhz When you looked at the total package the 3.8Mhz clocked system was faster.

Lets look a different way
You what to attach large memory to a Z80. How could ( want max options ) a Z80 bank switch memory. All the answers I have seen
1. a memory write
2. a IO write
3. using status pins the Z80 makes available and 1 and/or 2.

By todays standards Large memory is cheap and in logic speed to a Z80.
To bank switch what normally happens is some of the Z80's address lines are fed to a address changer/extender

The easy part is just use a fast ram to be the rom memory.
You said you wanted to download in to this fast ram, so if you can download in to one fast ram what is keeping you to more fast rams?

The bank switch is just a bunch of registers that are used to replace address lines with registers contents. Is 256 bank registers enough? Just take one of the fast ram chips like was used for cache memory back in early days( 30 ns) and use it as your bank registers.
Now the problem is addressing which memory location in that cache memory to use.
Take a second cache memory chip and tie it's address lines to the Z80 could effect bank selection.  going for the max, you have 8 data lines, 16 address lines and may like to add some of the control lines.  That's a lot of ram just to be a bank register select address generator. But if you think on it, those 8 data lines really need to go to the first cache chip as they can really only be bank switch data. If you look a lot of the cache chips were larger then 64k you can easily get  all the z80's address lines and some of the z80 control lines connected to the address of the cache ram. If a z80 control line is not on the NES socket you should not need it.
You now have a triple play
1. the second cache ram gets addressed and from it's data (you downloaded) supplies the bank select register address. (time probably less than 50 ns)

2. the bank select register address from #1 lets the Z80 read an write bank register contents when needed. The output data is the extra address lines.  (time probably less than 50 ns)

3. From #2 and the Z80 you now have the address for the LARGE ram pretending to be a rom.

Problems
Not reset: #2 has no power on reset. A down load is needed to set the data. The defaults for the bank selector it is pretending to be.
#1 needs data to make it act like a simple chip select. Unlike a normal chip select that misses a lot of address lines, any thing that can change #1's address lines needs data. If this was a non banked system. all it's data would be the same.
A bunch more to download, but you gain easy to change. It would be nice to have a program to build the data download for#1 and #2.

Questions?
Just an idea, have fun
C

 

[madshaman]

A quick note to C: he's working with a sega master system, not an NES.  The NES is a worse situation (it seems) as it's cartridges have a huge whack of different mapper chips.  Along the lines you suggest, the NES's 6502 does bank swapping via memory io, but the mappers are all different, map different subsections of the cartridge into different subsections of the 6502's (actually a combined 6502NMOS/2A03 sound generator /dma chip in one package) address space.  The protocols were all different too, it's reaching back too far, but the addresses written to were iirc protocol commands themselves, and also, (again memory fails me) I believe some mappers took action on reads, others writes. To make matters worse, the mapped io addresses were not always consistent between mappers.  (I know this because I'd written an NES emulator in the 90s, it was actually quite a complex little machine).

If any of the SMS cartridges have similar properties, the OP may need to have a micro able to react to a read or write at any arbitrary address and then emulate the appropriate mapper behaviour (which could involve waiting "x" cycles before remapping an address section) in order to have a generic cartridge capable of loading any arbitrary game with any mapper hardware.  Not completely trivial.

If the OP is interested in just programming an SMS, I highly recommend getting your hands on a sega sc3000 computer, it's almost the same as an SMS hardware-wise, but is a full fledged 8bit personal computer (I have one ;p, but don't get me started on my insane 8bit computer collection

P.S. hate autocorrect, it turned every "sega" to saga on me 

[pyroesp]

Just to clarify a bit more the mappers and Z80 I'm going to explain how they work.
I'm going to summarize mappers from what I've read here : http://cgfm2.emuviews.com/txt/smsmap.txt

All of those mappers stop at address 0xBFFF, which means that if the address of the Z80 is lower or equal to 0xBFFF you're (most likely) reading from ROM.
Some of the mappers can map an SRAM to 0x8000~0xBFFFF or even to 0xC000~0xFFFF (only SRAM). This is defined by the "config" register.
From the bigger ones, you can tell they can save 4 registers (if not 1 for the 128k ones), at 0xFFFC, 0xFFFD, 0xFFFE and 0xFFFF.
0xFFFC is like a config register. It tells the mapper if you mapped an SRAM at 0x8000 or 0xC000.
0xFFFD, 0xFFFE and 0xFFFF are used to set the value of A18~A14 (if it goes as high as A18).

The smaller ones (128k) with 1 bank only use 0xFFFF to set the value of the "higher address" lines. They don't map SRAM.
The bigger ones use all of the above. They can map ROM from 0x0400 to 0x3FFF, from 0x4000 to 0x7FFF and from 0x8000 to 0xBFFF and SRAM from 0x8000 to 0xBFFF and from 0xC000 to 0xFFFF.
I think, even though the SRAM is mapped from 0xC000 to 0xFFFF, if you write to 0xFFFC or above, you'll write in the mappers' registers.

The Z80 has 16 address lines, 8 data lines, 1 Cartridge Output Enable, 1 BusReq, 1 BusAck, 1 M1, 1 MReq, 1 RD and 1 WR. (Those are the important ones, I left a bunch of them out as they are not needed)
When reading or writing from/to memory, the Z80 will pull MReq and RD or WR low.
I can tell if it's writing those 4 registers in the mapper by checking following data:
- Is MReq and WR low ?
- Is address line > 0xFFFB ?

The Z80 reads and writes data in 3 clock cycles, but reads an opcode in 2 clock cycles. You can check if the Z80 is reading an opcode by reading M1. If you can trigger on the falling edge of M1, then you have 2 clock cycles to write data on the data lines. At the rising edge of the 3rd clock cycle it will read the data lines. MReq and RD are affected by this read operation.


@C:
I think your idea may complicate the process too much (or I'm not grasping the idea).
If I can have 4 variables in a CPLD, I don't need the extra cache. Whenever the Z80 tries to read a byte from ROM, just OR one of the variables to the higher address lines and that's pretty much it.

@madshaman:
I'd like to make a program for the SMS, but also play some old school games .

[madshaman]

Sounds like the mapper register addresses and function are all consistent, much easier to handle.  Contrast to this: http://tuxnes.sourceforge.net/mappers-0.80.txt

I only ever implemented MMC1 in my emu, imagine supporting all those in hardware ^^

I also have an SMS, my fav games: wonder boy iii: dragon's trap, phantasy star, space harrier and space harrier 3D, outrun 3D, kenseiden, and spellcaster.  All great :-)

[C]

Hi
I do not know your game consoles, Helped my boss build his first Z80 back when just the Z80 chip cost $500. The bad news was the chip fried. The good? By then the replacement was just $260.

Ok
  256 K x8 cache ram chip
By my count that is 18 address lines. That leaves 2 if you connect them all.
If you were to connect one to M1 you would have 8 bits of data out of the ram that could be different if it was an M1 cycle or not. The data could be different for any address. In simple terms you could take one bit on the output and use it as a chip select. Think a second, a chip select anywhere in memory. Of any size you want. Want the chip select active in many different locations all with different sizes from one address up to 64K not a problem. It's all in the data you write to the cache ram chip. The 8-bits of data out could be 8 chip selects.
The example I made I used them as an address. 8-bits = 256 addresses.

For the Z80 to use more memory, it takes two things, careful programming and a way to change the memory map. I is not a good idea to change the memory map and have SP point to rom for example. In simple terms, a memory mapper lies the the processor, processor wants ____ it gets _____ with out knowing. Only two simple ways to change the map setting with a Z80, a write to io space or memory (just thought a third, later) most of the ones i have seen the instant that write happens the map settings are changed.
Instead of an an 8 bit latch at address ___ that the cpu can write to control map switch, I used a fast ram chip. I now have a whole bunch of 8-bit latches. I added a problem in the process, the separate 8-bit latch's data was available all the time. If you have 3 separate 8-bit latches you could have 3 maps. One mite control the 0 to 4k area, the second the top 8K, the third some place else. There is what could be called a chip select to identify when to enable each one. So 8-bit latch with a chip select VS Ram. For Ram the work here it needs to be very fast so that it can get the correct data visible to be used just like the 8-bit latch when needed. And it needs to allow the Z80 to write to it for map setting changes.
In the old days ram was just too slow, but cache ram's sole purpose is to be smoking fast so normal memory does not need to be read again.
Here we have two in series. So when the z80 goes to read or write, instead of a chip select delay and memory delay, you have cache one ram delay, cache two delay, memory delay. Can you get all three done in time to keep the Z80 happy. What I think is that with todays fast chips, stacking the deck by using cache ram chips to gain more time you can.

 C

[C]

Lock in
  here is a simple one I got cough once with,
Take a standard static ram chip, lets put it in a socket to make it easy to see.

Un plug the chip and put it on a board that can plug back in. The board has some inverters so some of the address lines go through an inverter, Does it still work if you do not create a timing problem.

At the socket where the ram chip was is no different! All the inverters do is scramble the data in the ram chip. On power up both have random data. So both have to be written to for good data, so the initial data gets scrambled the same as all accesses.

C

[lgbeno]

Cpld is non volatile so unlike an fpgas, it will retain its configuration without the use of a flash loader.

I've used altera mainly in the past just because it was popular at the company I worked for.  Sorry wasn't aware of the terasic kit being phased out, that's is unfortunate!  I found a cheap Chinese kit on eBay:

http://item.mobileweb.ebay.com/viewitem?itemId=330813186044&cmd=VIDESC

Otherwise if you feel like trying lattice, they have some good, inexpensive kits and better documentation.  Some developers don't like their tools as much but this is a basic cpld so I think you would be fine.

http://www.mouser.com/Search/m_ProductDetail.aspx?Lattice/LC4256ZE-B-EVN/&qs=6HzElnOpChP0mJ6ydbqzwA==&gclid=CKfF1Pqeq7YCFdOHMgodGmYAnA

Writing either Vhdl or verilog is a little bit of a learning experience because it implements parallel logic instead of the sequential execution that a CPU does.  It is very powerful once you learn to do it.  Vhdl is very strongly typed so it is extra annoying however with verilog, you get more rope to hang yourself with.  I've used both, I like verilog better.  I wouldn't consider myself an expert by any means either but I'm sure there are some on the forum.

[lgbeno]

Well I guess the forum cut out my links and the other half of my post...

What I was trying to say is to look for "Altera MAX II EPM240 Core Board FPGA CPLD Development Kits JTAG & USB Blaster" on eBay.

Or if you would like to try lattice, they have inexpensive kits with better documentation:

Search:
ispMACH 4256ZE Breakout Board


Just noticed too that dangerous prototypes has a pretty good reference for those looking at learning cpld.

Look for "CPLD: Complex programmable logic devices" on their site.

In general, learning hdl is not easy most experiences programmers.  If you this about it, it is a very different paradigm you are describing a parallel execution of logic happening at each clock cycle as opposed to a sequential order of operations.  The parallel aspect makes it very powerful those for these cycle by cycle applications.  Vhdl is very strongly typed so it is very frustrating for starters.  Verilog gives you much more rope to hang yourself with.  I prefer verilog over Vhdl and wouldn't be surprised if your past experience was with Vhdl.

[C]

ok, lets see if I can get across what I am seeing, I will probably fail.

In simple terms you want some hardware that can plug in to that connector.
You want to soft load that hardware so that it acts like the original.
That connector is complete enough that almost any thing is possible.
  It would be very easy to quickly copy the hardware from my very old lobo computer and gain the hardware needed for a hard drive interface. You could hang a terabyte each of ram and rom.

My idea will not work, it is missing some parts.
I do not think you could get any non reprogram able setup to work for all possibilities.
If you do not know how a specific thing plugged in to that port works, a soft copy version is probably 0.   
The Up side
These were commercial, to make money they had to be simple.
You can probably use normal programming practice to help identify how an unknown works.
The programming and hardware are both on the plug in, that hides some things as well as gives a whole to find out how a plug-in works.

Using a fpga for this is pre computing some logic and then trying to compute the rest in real time. I do not think you can do this with out lots of cash. The more you can shift to the pre computing side, the less critical the real time part becomes, saving cash.
The good thing is that there are a limited number of pins and some are simple logic of some other pins.

Where my idea fails is in the reset area and the crazy things logic can do. Put the two together an you may have a winner.The big thing to remember is that you do not care how scrambled the data is in the soft memory it it appears at the connector properly it good.
extreme example: say the soft memory was huge, You do not care how the cartage data gets splattered in the huge memory as long as it comes out correct. Compared to when the system was built very Huge fast memory exists cheaply. The original cartage may map ____ to  ____ in the rom in a nice neat faction. you really do not care how it gets mapped in to the soft ram as long as it is unique and appears at the connector the same as before.
 

Say you build a soft board that has some soft programmable logic and add my brute force fast ram stack. Ie dump this pre computed data in the soft logic, dump this pre computed data in brute force ram then from the data connector load the rom contents.
In this case the cpu your looking for is for the commuication link to the pc and to load the data, While the game is runnin the cpu is idle.
Now if you look at a processor like the stm32f3 or stm32f4 you may think that it could do the above, but with timing that tight i think it would fail.
The unknown plug-in
With a fast USB interface the stm32f3 or stm32f4 may be able to be a logic analyzer. Think very huge, A pc program sifting through the logic analyzer data of the program running on the z80 could see the z80  asked for data from this address and the first time it got ___ the second it got ___. If the pc program then looked for writes between the two? Some would be in the known category. the others, you would have the data to figure it out but it may be hidden and not worth the time involved.

C 

[AndyC_772]

What I was trying to say is to look for "Altera MAX II EPM240 Core Board FPGA CPLD Development Kits JTAG & USB Blaster" on eBay.

The EPM240 is a very small device. I've used them many times, but often end up running low on logic and wishing I'd used something a bit bigger.

I'd be more inclined to suggest using an FPGA with a serial EEPROM attached. You just program the EEPROM using the USB Blaster cable, and the FPGA automatically configures itself by reading the EEPROM data at power up. The combination of the two chips behaves very like a CPLD, but with a great deal more logic and other hardware (PLLs, memory, DSP blocks) available.

[lgbeno]

Pyroesp FYI I sent you a pm if you don't check those often.

[lgbeno]

What I was trying to say is to look for "Altera MAX II EPM240 Core Board FPGA CPLD Development Kits JTAG & USB Blaster" on eBay.

The EPM240 is a very small device. I've used them many times, but often end up running low on logic and wishing I'd used something a bit bigger..

There's also a epm1250 kit on eBay.  Otherwise there's epm2200 in general I agree a fpga could do it all.

[andersm]

I'd be more inclined to suggest using an FPGA with a serial EEPROM attached.

For this particular application, a CPLD with 5V-tolerant I/O is better suited. For learning programmable logic, an FPGA board will be more versatile.

[pyroesp]

I'm not too fond of buying stuff from China.
The first thing I bought (3 axis accelerometer) never came and the second thing I bought (4 8x8 LED Matrix) came after probably a months if not more...

I have worked with FPGAs (Spartan 3E board) in VHDL. It wasn't too bad, but the fact it's parallel execution instead of sequential was tricky to work with.
I'm used to programming in C, so sequential execution.

The USB Blaster is 300$... That's a little expensive  .

PS: Wonderboy III is awesome, best game ever. I Love Alex Kidd too.

[AndyC_772]

The genuine Altera item is, but you can get a perfectly functional clone for 1/10th of that price - provided you don't mind buying stuff off Ebay from China.

I'll get my coat...

[nctnico]

What I was trying to say is to look for "Altera MAX II EPM240 Core Board FPGA CPLD Development Kits JTAG & USB Blaster" on eBay.

The EPM240 is a very small device. I've used them many times, but often end up running low on logic and wishing I'd used something a bit bigger.

I'd be more inclined to suggest using an FPGA with a serial EEPROM attached. You just program the EEPROM using the USB Blaster cable, and the FPGA automatically configures itself by reading the EEPROM data at power up. The combination of the two chips behaves very like a CPLD, but with a great deal more logic and other hardware (PLLs, memory, DSP blocks) available.

Most modern FPGAs are not 5V tolerant, need multiple voltages and the EEPROM may take too long to load. The Xilinx CPLD I recommended earlier can be programmed (in circuit) with a $40 USB programmer from Ebay. It doesn't get easier.

[pyroesp]

I looked through farnell.be dev boards and I found 3 cheap boards. Can some of you tell me if they're good or bad ?

CPLD board from Lattice : http://www.farnell.com/datasheets/1673546.pdf

FPGA board from Lattice : http://www.farnell.com/datasheets/1673553.pdf

Second FPGA board from Lattice : http://www.farnell.com/datasheets/1673554.pdf

They don't have any FPGA board anymore. They'll get 3 from the first FPGA board on April 7th, and 6 of the second FPGA board on June 1st.
They all are programmed through USB and have a JTAG connector, so I suppose I'll be able to program most of the Lattice CPLDs/FPGAs.

What do you guys think of the boards ?
Those are just toys, I know, but if I can learn how to use CPLDs and/or FPGAs and I can program most if not all Lattice devices through the JTAG port, it's a win-win, right ?

@nctnico: Can't you program all, if not most of, the CPLD and/or FPGA in-circuit ?

[amyk]

The genuine Altera item is, but you can get a perfectly functional clone for 1/10th of that price - provided you don't mind buying stuff off Ebay from China.

And for a little bit more you'll get Lattice, Xilinx, and two logic analyser clones too.

There are probably ones including a DSO/DMM too...

[nctnico]

Those are just toys, I know, but if I can learn how to use CPLDs and/or FPGAs and I can program most if not all Lattice devices through the JTAG port, it's a win-win, right ?

@nctnico: Can't you program all, if not most of, the CPLD and/or FPGA in-circuit ?

An FPGA usually needs an external flash/eeprom device. Some FPGA's have a flash chip inside the package. You'll still need a way to get that chip programmed. The problem with JTAG is that it only specifies the electrical interface and how the shift registers are organised. Beyond that everything is proprietary. If you want to program Xilinx chips, you need a programmer suitable for Xilinx' software. In some cases you can generate a file which basically is a recording of all the required JTAG operations which can be replayed by a universal programmer.

There is not really a need for a development board. The XC9572XL devices also come in a PLCC package which you can use on vero board with a socket:

[pyroesp]

nctnico, isn't that possible with Lattice CPLDs ? I'm sure there are Lattice CPLDs with a PLCC package.
If I buy one of those CPLD boards I can learn how to program that particular CPLD.
I can later make a board like you've made, with a PLCC socket and program that CPLD with the JTAG of the Lattice board.
I suppose that's something that could be done...

PS: Nice little board btw, looks very versatile.

[nctnico]

I don't see why it is not possible with Lattice CPLDs.