The best way is actually not sharing that SDRAM on the board directly. Instead it might be better to hook the SDRAM solely to the FPGA, implement a bus matrix and SDRAM controller in the FPGA, and expose one of the bus matrix slaves to the ARM core.
Or just bump up to a Zynq, which allows FPGA matrix access the memories attached to the ARM side over the AXI port.
+1 for @technix solution, if you have an external ARM MCU and a separate FPGA and (S)DRAM, is the best way to do it, one can even map the FPGA registers as memory and be done with it. It's a hassle on the digital design side, but is doable.
If this is no academic project, then for all the practical applications the modern FPGA with embedded ARM cores are a much better way to do it, and you have them in all speed and strength grades. And of course, if ARM core isn't a must have, there are the strange animals being developed by ALTERA-Intel matrimony, but for the moment are not mature or supported enough.
Best of luck,
DC1MC