Simple FPGA problem - Error when assigning - Verilog

[pigtwo]

Hey guys.  I was just attempting a very simple design for an FPGA(Just a d flip-flop) and I am getting a weird error.

Every time I try to assign something, it tells me that the first thing is unexpected.  I'm sure it something simple, but I just can't seem to see it.

Here's my code:

Code: [Select]


module dflipflop(

input wire clk, data,
output wire out1

    );


wire q1, q2, q3, q4, q5, q6, q7, q8, q9, q10;

assign out1 = q9;

assign q1 = data ~& q2;
assign q2 = !clk;
assign q3 = q1 ~& q2;
assign q4 = q1 ~& q5;
assign q5 = q3 ~& q4;
assign q6 = clk;
assign q7 = q4 ~& q6;
assign q8 = q6 ~& q7;
assign q9 = q7 ~& q10;
assign q10 = q8 ~& q9;


endmodule
And this is the error I'm getting:

Code: [Select]

ERROR:HDLCompilers:26 - "dflipflop.v" line 33 unexpected token: 'data'
ERROR:HDLCompilers:26 - "dflipflop.v" line 35 unexpected token: 'q1'
ERROR:HDLCompilers:26 - "dflipflop.v" line 36 unexpected token: 'q1'
ERROR:HDLCompilers:26 - "dflipflop.v" line 37 unexpected token: 'q3'
ERROR:HDLCompilers:26 - "dflipflop.v" line 39 unexpected token: 'q4'
ERROR:HDLCompilers:26 - "dflipflop.v" line 40 unexpected token: 'q6'
ERROR:HDLCompilers:26 - "dflipflop.v" line 41 unexpected token: 'q7'
ERROR:HDLCompilers:26 - "dflipflop.v" line 42 unexpected token: 'q8'

Again, I'm sure it's something stupid and obvious, but just can't seem to figure it out.

Thanks!

[jmole]

Don't use the word "data" in your code

[pigtwo]

I changed it but I'm still getting the same error.

[pigtwo]

Ok, I seem to have figured it out.

Apparently it didn't like the '~&' operator.  I misread this off a website and thought it could be used as an NAND.  It seems to only be an unary operator. 

[FrankBuss]

Right, but you can use the concatenation operator to implement the NAND. And there is a missing "endmodule". "data" should be no problem. This compiles in Quartus:

Code: [Select]

module dflipflop(
input wire clk, data,
output wire out1
);


wire q1, q2, q3, q4, q5, q6, q7, q8, q9, q10;

assign out1 = q9;

assign q1 = ~& {data, q2};
assign q2 = !clk;
assign q3 = ~& {q1, q2};

endmodule

Of course, it doesn't make sense, because you didn't assign a value to q9. And I would use the edge triggered commands (posedge clk) for implementing a d flip-flop, as you can see at http://en.wikipedia.org/wiki/Verilog

[pigtwo]

Ah, I see, I was wondering how you would use that. 

Yeah, I was pretty sure I was doing this in a stupid way.  I am extremely new to Verilog.  I was actually doing it just to test using modules.

[free_electron]

wow. what are you smoking ?

why do you want to hardwire logic this way in verilog ? this is netlist format... that is not the intent of verilog.
and what'swith all the wires.

you dont need to design a 'd-flipflop' those are avaialble in the fpga

module dff(input clk , din, rst , output reg dout)
always @(posedge clk) begin
    dout <=din;
   if (rst) dout<=0;
end
endmodule

there you go

whenever a clock occurs dout becomes equal to din
if RST is active then the output is reset.

[marshallh]

this is the way they teach verilog at many schools...

Those who can't do, teach, those who can't teach - teach gym

This sort of approach was only necessary more in the early days of asic design.. when your ASIC vendor provided you with a set of cells and you had to boil everything down into them yourself.. nowadays synthesis tools are largely smart enough to take care of that abstraction. If I'm wrong about this please correct me... There is not much info out there

If you're going to go down this low of a level, always study the FPGA fabric design so that you know how your logic will be synthesized.. and then CHECK the actual result in the vendor's technology viewer!!

[fpga]

I just couldn't resist helping out on this one!

The correct way to describe a D flip-flop (without a reset) is:

module dflipflop(
    input      clk,
    input      d,
    output reg q);

    always @(posedge clk)
        q <= d;

endmodule

However, this is the wrong thought process in modern digital logic design. In the old days of the 1960's through 1980's, most digital logic was reduced (hand optimized) to gates and flip-flops. Since the arrival of programmable logic, PALs, GALs, CPLDs, and FPGAs, as well as ASIC technology, tools have been developed that permit coding in higher, more abstract level, and letting the tools optimize to the lowest level, which in programmable logic is generally lookup table based cells. This abstraction is similar to writing software in C, C++, or Java and letting the compiler create the assembly and/or machine code for the CPU.

You need to think in terms of synchronous parallel signal paths. An input into your design will pass through one or more stages of registers and combinatorial expressions before the final register and output.

<input> -> <reg> -> <combinatorial expression> -> <reg> -> [<cobinatorial expression> <reg> ...] -> <output>

You do think of multiplexers, decoders, finite state machines, etc., but you code at an abstract level that describes the design's intended functional behavior, while leaving the tools room to optimize for the intended target device. In synchronous design you think about what happens between one clock cycle and the next. Do not implement asynchronous paths in your design unless you have a good reason for doing so, you know what you are doing, and you provide a good comment explaining the fact.

Doing hand optimization only obscures the code's intent by making it more difficult for you and a future reader of your code to understand what it is supposed to do as well as it may also force the tools you synthesize your design in a less than optimal manner.

Also, don't forget simulation. Learn how to use Modelsim and write testbenches.

As for the comments about academia -- I have come across many examples on the web of lecture material as well as college textbooks which clearly demonstrate a total lack of the author's or lecturer's understanding in the field of modern digital design. They will waste many pages on describing how a 7400 NAND gate is implemented by analyzing the "equivalent transistor circuit" in the datasheet, then go on to great lengths coding a netlist in Verilog to instantiate and wire up all the individual gates and registers to implement an adder or mux. When these students enter the work force, they are totally lost and need to be re-trained from scratch. A significant percentage of the faculty teaching engineering these days never built a circuit or wrote a program in their life. Worse yet, some of them will grade you poorly if you implement circuits correctly and not the way they lecture. I've been there and it was a very frustrating experience. There are exceptions, but they generally had a career in the industry or a research lab before becoming lecturers.

Fortunately, today the technology is mature and there is a great wealth of information available, much of it free as well as very capable free of charge software tools and low cost development boards from all of the top vendors.

A few links:

http://www.xilinx.com/support/documentation/application_notes/xapp143.pdf

Google for: Xilinx Synthesis and Simulation Design Guide

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?GSA_pos=4&WT.oss_r=1&WT.oss=verilog%20design

http://rainier2.latticesemi.com/cs.html?url=http%3A//www.latticesemi.com/lit/docs/manuals/fpga_design_guide.pdf&charset=iso-8859-1&qt=verilog+rtl+design+guide&col=faqs+public&n=1&la=en

http://www.actel.com/documents/hdlcode_ug.pdf
http://www.actel.com/documents/vlogsim_ug.pdf

Plus all of the major vendors have tutorials, example designs, and some have free web based training.

My suggestion is to find simple example designs in your chosen FPGA that implement similar functions or interfaces that you are trying to implement, play around with them, understand what they do and why they are implemented the way they are, and go from there.

Good luck and most of all, have fun!