STM32F0 timers and adjustable delay before DMA burst

[voltsandjolts]

FFS, CubeMX you piece of shit.

Can the Cube.
Go bare metal
https://github.com/ataradov/mcu-starter-projects

[Psi]

FFS, CubeMX you piece of shit.

Can the Cube.
Go bare metal
https://github.com/ataradov/mcu-starter-projects

Yeah, it was only a test project to try out a few different ways of doing things and seeing what worked.
I was expecting cubemx would save time, i was wrong.

[wek]

What is "10us burst of DMA to GPIO"?

JW

[Psi]

What is "10us burst of DMA to GPIO"?

JW

A DMA copy Memory-to-GPIO with 10us of width between gpio pin state changes. (100khz DMA transfer).

(Its actually ended up being 35khz now, but yeah, that's what I was meaning when i said that)

[aeg]

When you say "burst" do you mean a single DMA transfer, just one write to the GPIO register?!

[Psi]

it's around 11 DMA writes to do burst of digital data I need on the gpio.

I currently have it working on STM32F072 more or less. There is some miner jitter which i think is just interactions with the bus when multiple DMA transfers want to happen at once but can't, so one has to wait.
I'm using all 7 DMA channels that the F0 has. 1 was already used for ADC, 4 are for DMA writes from 4 timers,  and 2 are used for a single byte DMA write on compare match to start 2 of the timers. The other 2 are started by an external link between CC output pin and edge detector trigger input pins.

Funny thing is you can't actually do it on the STM32F407 dev board i have because only 2 timers have access to GPIO via DMA.
(Only 1 of the DMA controllers has access to that bus).

But for now, it's working on the STM32F072 well enough for me to proceed to the next step.
I may come back to this later and try a different approach using 4 SPI outputs.

[pcprogrammer]

I may come back to this later and try a different approach using 4 SPI outputs.

That was my first thought when I read:

it's around 11 DMA writes to do burst of digital data I need on the gpio.

It needs 4 SPI interfaces of course, but has less traffic on the bus.

[Psi]

I may come back to this later and try a different approach using 4 SPI outputs.

That was my first thought when I read:

it's around 11 DMA writes to do burst of digital data I need on the gpio.

It needs 4 SPI interfaces of course, but has less traffic on the bus.

Yep but afaik no STM32 F0,F1,F2,F3 have 4 SPI outputs, would have to move to F4/F7/H7 which is kinda overkill unless its the only option

One DMA and 3 SPI might be an option though.

Also SPI makes it a bit more tricky. I want to generate 4 separate busts of digital data, however the first pulse is at a different voltage level to the rest.  Using DMA to GPIO makes it easy because I can use 8 GPIO outputs to generate 4 data bursts that can have two different voltage levels.  But I think I can probably use 4 compare outputs for the first pulse and SPI for the rest. So might be doable.