Stm32f103 not stabile data clk out

[matise]

Hi. Im using this f103c8 to a dds9850 and the problem is that the data and clk stream to dds is not stabile.
Its Moving around so the dds is also totalt out of stability.
I changed from internal to external crystal but its the same problem.
I use 2Mhz freq in stm32.
Anyone has an Idea for me to try here?

[HB9EVI]

can you pse specify the problem more detailed. what do you mean with 'not stable'? do you have some scope screenshots?

a schematic would help too...

[Doctorandus_P]

STM32 uses a PLL derived clock, and they simply do not care about phase noise.
They only care to pump up the clock frequency with the PLL to a high value, and with just enough accuracy for the CPU to be able to run reliably from it.

You can try to use a crystal with a higher frequency, so the PLL has to multiply less, but if you want a low jitter clock for your 9850 then you probably need to find a better clock source.

Depending on the quality and stability you need, this may become difficult.
For example, a TCXO can have pretty good long term stability (0.1ppm), but adjust the output frequency in small steps when the temparature changes, and this may be totally unacceptable.

Also, If you're new to this I wonder what gear you use.
Are you measuring the frequency stability of the STM32 or of your gear?

A few years back Dave Jones ( Owner of this forum, makes EEVblog) did a video about PLL instability in a popular Rigol Scope.
Rigol responded by "fixing" it in software, which is of course not possible, but it was a partial solution which brought the jitter a bit down.