> 1- Since the RX fifo is shared, is there one POP register for all EPs? If yes, which one?
The FIFO scheme in the Synopsys OTG module is bizarre (and probably tries to cater for memcpy() or similarly working DMAs in mcus other than STM32). There is no single PUSH or POP register, instead, a whole address range functions as such register - 4kB each endpoint's Tx, and, as you've noted, Rx is shared, so probably reading from any of these address ranges would work; but according to Data FIFO (DFIFO) access register map table you are supposed to read from the same range for given endpoint as you write to.
Note, that anything related to FIFO is word-based - you must access it as aligned words, and every register/bitfield related to FIFO size or occupancy is in words (whereas data-transfer registers are in bytes).
And finally, mind the erratum which mandates a packet's worth of FIFO being read/written at once, without being interrupted by accesses to some other OTG registers.
> 2- What's the minimal initialization needed to start the module aside from enabling clocks, configuring PA11 and PA12 pins to alt-func push-pull outputs with AF10 and enabling the OTG_FS interrupt Nr 67 in the NVIC?
You probably figured that out already - clocks have to be set up in RCC and running, beforehand. start by disabling the integrated pullup by setting USB_OTG_DCTL.SDIS, you need to enable PHY by setting USB_OTG_GCCFG.PWRDWN (very weirdly named bit, btw.) and you probably want to force the device mode by setting USB_OTG_GUSBCFG.FDMOD. You'd also need to set up the FIFO sizes. Finally you enable interrupts and the integrated pullup by clearing USB_OTG_DCTL.SDIS.
For a more generic startup you may want to do things like resetting the module beforehand, in some "higher" STM32 model you may need to select FS/HS etc.
> 3- What to do when these interrupts fire: RESET and ENUM DONE?
You may want to read the USB (v2.0) specification. It's quite badly written and not an easy read, but at least skim it through. In this particular case, you may want to look at 7.1.7.3 Connect and Disconnect Signaling and 7.1.7.5 Reset Signaling.
From firmware perspective, the USBRST interrupt is a good place to reset the whole software stack (i.e. remove/reset any outstanding status from previous communications) and to enable EP0 to listen to SETUP packets. The ENUMDNE fire when the FS/HS chirp handshake is over; but in 'F411 is irrelevant as the device speed is there fixed to FS.
> I'm getting "Int - Rx FIFO not empty" continously at an astonishing speed!!!
The mechanism behind RXFLVL interrupt is weird, more complicated than it would appear at first glance (for reasons both historical and to cater for various configurations of the module, e.g. using the internal DMA (which is not present in 'F411's incarnation of this module)), and the main problem is that it's very inadequately described in the documentation.
This interrupt does not indicate "Rx *data* FIFO level". Rather, between the USB core and registers there is a small FIFO conveying events from the Rx portion of USB core to the processor. This interrupt indicates, that this FIFO has some event in it, and you pop these events from this FIFO by reading OTG_FS_GRXSTSP. Read description of this register for Device mode. Popping some of the events triggers other interrupts, see description of the PKTSTS field of this register - for example, popping OUT transaction completed triggers the respective OTG_FS_DOEPINTx.XFCR interrupt.
JW
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