STM32N6 Series

[ali_asadzadeh]

Finlay we have Cortex M55 parts from ST,Hopfuly we see some from NXP too!!! And they got 800MHz clock with a 1GHz clock for ST Neural-ART accelerator! when we do see TQFP parts and the value lines of this family? what do you plan to build with them?

https://www.st.com/en/microcontrollers-microprocessors/stm32n6-series/documentation.html

[ali_asadzadeh]

They claim it has a high res timer too,But I can not find any info in the user manual, I hope to see one or two also a mipi lcd interface would not hurt too.

[mark03]

They are impressive-looking parts.  Quite an errata on the N6, which might explain why it spent years stuck in limbo.  And that doesn't include the various accelerators, which may also have or have had issues, but we wouldn't know because they are secret peripherals.

Personally, I would be more interested in an M4 -> M55 upgrade for the flagship low-power series (U5), as that is more of a lateral move in processor.  Basically, give me Helium with all the other low-power goodness.  The neural accelerator is interesting, but only to the extent that it can be abused.  If it can only be operated with vendor tools in ways that the vendor intends, then as far as I'm concerned it's useless silicon that I'm forced to pay for.  But maybe that's just me.

If I'm looking for high performance (w/o regard for power consumption) then I want the M7 -> M85 upgrade.  This is rumored to be on its way, but sounds highly ambitious (18 nm process, phase-change memory), so I don't expect it any time soon.

I do hope the N6 is a runaway hit for ST so it can help fund development of the parts I actually want to use   Or, perhaps we will have compelling RISC-V MCUs (in segments other than "value") by then.

[ali_asadzadeh]

I'm waiting for the NXP to show their 1.5GHz version

[hans]

Well I just had a quick peek at the reference manual for this chip.
Which BTW is 95MiB and 4692 pages long

But among all that information, implementation details on the NPU is very sparse. It's mostly concerned with how models and data are streamed, activated, chained, and processed. Lots of juicy mentions on a 14.4 Gbyte/s memory bandwidth between local SRAMs (16 byte wide access). But not a single mention of any RTL .
I reckon ST will distribute any NPU referencing code via a static library to protect their own IP..

Quite remarkable since the H264 encoder and Gigabit phy have received lengthy chapters, but I reckon those are probably some standard Synopsys (or alike) IP.

[ali_asadzadeh]

I think we would see lot's of Cortex M55 parts in 2025, I have seen devices from  ambiq  AP510NFA-CBR ,Alif Semiconductor ,Infineon PSOC Edge and Himax HX6538-A
and all of them uses Ethos-U55 and only ST has developed it's own NL core, so my guess is the tredn would go to Ethos-U55.