TDMA Phy MAC interface

[rakeshm55]

Hi all,
 I am trying to implement a PHY MAC in Virtex 6. The communication scheme used is a custom based TDMA scheme....

I would like to know on what should be the nature of interface between PHY and MAC given that the scheme is TDMA...
Take data receive scenario
1st scheme proposed is
1.  PHY maintains the time sync and all other layers are oblivious of the slot timing(say 1ms).
2. When ever a packet is received PHY will dump data into a FIFO 1K X 8 with Length of packet as first 2 bytes representing packet length.
3. MAC will read the Length first and read out all the data upto  informed length and process it .....
4. once the processing is complete returns and check whether fifo if is not empty read length and read packet.....
Packet boundaries are maintained using the length information

in this scheme time information is with PHY and MAC has no sense of time in the receive path

2nd scheme proposed Receive channel.....
1. PHY writes data into a FIFO.
2. PHY informs MAC with data valid signal informing that there is valid data in fifo (This is the 1ms sync signal)
3. MAC starts reading data
4. PHY will not write the next slot data until FIFO is empty.
5. MAC detects the packet boundary using empty signal of FIFO.
Data valid signal will be issues after 1ms intervals so that MAC works on a time sync manner


which is the right way to work in a TDMA scheme??

Please suggest