An EPROM is a static memory device like an SRAM, all the address lines are decoded at the same time and nothing else affects them.
Flash is more like DRAM by being divided into pages. The controller has to send a command to open a page (similar to RAS for a DRAM), and then it can read out of that page.
So I can't simply apply an address to a parallel flash device and have the data appear on the data lines like happens with an EPROM??? This could be a deal breaker. 
No - there's no problem whatsoever in reading a parallel flash, as the ones you mentioned in your OP.
The highlighted statement from helius is misleading at best - if not wrong.
The data sheet for those parts makes it very clear.
The difference for top and bottom boot is that some shorter sector is mapped to high and lower addresses (with some resulting hole) to facilitate storing a boot loader - and updating the rest of the FW - without wasting a bigger than necessary area.
For word mode A18-A0 are used, for byte mode A18 to A-1.
To program them, as for any other flash of this type, the algorithm specified by the manufacturer must be accurately followed.