Trigger an FPGA on rising edge of high frequncy signal

[msngupta]

Hi,
I have an FPGA evaluation board with Xilinx Spartan-6 XC6SLX9 and a 100MHz oscillator for clock. I need to trigger my FPGA with one of the rising egdes of a a square wave which is around 250MHz. Can I directly input the signal (since the signal has higher frequency than the clock itself) and use it as a trigger or do I need to use some frequency division before sending it to the FPGA?
The datasheet (http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf) lists many frequencies, not sure which parameter I need to look for.

Any clue regarding this will be really helpful.

I don't have the 250 MHz signal currently otherwise I could have directly checked if it works.

Thanks,
Sainath.

[nctnico]

You can use an internal PLL to make a higher frequency signal and use that to sample the incoming signal. Maybe you can even use the IOSERDES block to sample at several hundred MHz.

[Marco]

What is supposed to happen if you get 2 triggers within 1 clock cycle?

[exmadscientist]

The relevant tables in DS162 are 29, 35, 37, and to a lesser extent 40.

I do not think you will have much trouble getting a 250MHz signal into a Spartan-6. As others have said, the issue will be what you do with it and the timing relationships between your this signal and your 100MHz clock. What is the edge frequency of the fast signal? What's supposed to happen when two edges occur in quick succession, or is this not possible?

Two external solutions are a '123 retriggerable monostable, which can create a longer pulse on edge detection, or a '74 configured as a RS flip-flop (set on pulse, reset by FPGA on processing). Both have their advantages and disadvantages.

It really all boils down to what you need to do with the fast pulse signal.

[John_ITIC]

If you just want to find out whether the external signal has gone high then it is easy. Just put two synchronizer registers on an input pin and clock it into your 100 MHz clock domain. https://www.google.com/?gws_rd=ssl#q=fpga+synchronizer

[msngupta]

The signal I was talking about is a 250 MHz clock signal provided by some other IC in the circuit. I want my FPGA to change the state of one of its output on rising edge of this signal (please check the image attached).

[nctnico]

In that case you'll need to clock (part) of the FPGA from that 250MHz clock and possibly also some logic inside the FPGA. Xilinx has several application notes on how to make sure the internal clock has a defined phase relation with the external clock.