Variable Clock Divider

[Sparky49]

I'm in the process of designing a project with a Cyclone IVE. Part of this requires creating an adjustable clock to put out. I've so far settled on using the ALTPLL from the Altera IP Catalog to achieve this ( in reconfigurable mode). However, I still need to calculate the values for M, N and C in the PLL for a given frequency, where

Fout = (Fin * M)/(N*C)

Fin = input freq
Fout = output freq
M = counter (multiplier) part of clk feedback
N = counter (divider) part of clk feedback
C = post-scale counter (divider)

But I am at a loss as to how I could calculate these three values. I also have a nios ii processor running on this device, so an implementation could easily be done in C rather than a HDL. How could I arrive at these three values to give an accurate, given Fout when I have a fixed Fin?

Many thanks in advance.

[hamster_nz]

Code: [Select]

  f_in = ????  << Your input frequency
  f_Vco_max = ???  << From the datasheet, for your FPGA's speed grade
  f_Vco_min = ??? << From the datasheet, for your FPGA's speed grade

  for all possible m values
     f_Vco = Fin * m
     if f_Vco >= f_Vco_min and f_Vco <= f_Vco_max then
       for all possible n values
          f_out = f_Vco / n
          if f_out = F_desired then
             write "Values are " m " and " n
          end
       loop
     end
  loop

If you intend to use the post-scaler, you will need a third loop to try different 'C' values.


Edit: Having a quick look at the data sheets, the PLL internal VCO operating range is 600 — 1300 MHz, but don't  trust me on that one.