Verilog, binary to Gray code converter

[sevenofnine33]

Not sure if this is the section to ask, but I am a beginner and don't know much, so I would appreciate the help.

I am designing a binary to Gray code converter. This is my main code:

module gray_code (bin_num, Gray_num);

input [3:0] bin_num; //binary input
output [3:0] Gray_num; //gray output


assign Gray_num[3] = bin_num[3];
assign Gray_num[2] = bin_num[3]^bin_num[2];
assign Gray_num[1] = bin_num[2]^bin_num[1];
assign Gray_num[0] = bin_num[1]^bin_num[0];

endmodule
And this is testbench:

module gray_code_tb;

reg [3:0] bin_num;
wire [3:0] Gray_num;   
integer i;

gray_code DUT(.bin_num(bin_num),.Gray_num(Gray_num));

initial begin

for(i=0;i<16;i=i+1)begin
    bin_num=i;
    $display("BIN = %b   GRAY =%b", bin_num, Gray_num);
end
end

endmodule
The output I get after simulation is:

BIN = 0000   GRAY =xxxx;
BIN = 0001   GRAY =xxxx;
BIN = 0010   GRAY =xxxx;
BIN = 0011   GRAY =xxxx;
Why is it showing all x for Gray code?

[sevenofnine33]

Found the problem. In my simulation the time didn't pass. Adding #50 after bin_num=i fixed it.