Have fun with it. Slap down an FPGA and build your own DDR controller. But then I'm a digital design puke so maybe you'd rather skip it and not invest that much energy into this aspect of your project....I get that.
DDR controllers can be non-trivial things to design. Every project I've ever worked on had a guy that was dedicated to nothing but designing the memory controller. Typically you'll find separate modules / blocks that handle things like refresh, and an arbiter that coordinates with it to mux in "client" requests to access the memory. Yes, there needs to be some buffering someplace. How much and where to put it is application and implementation specific. Will need to do some calculations on access latency, time to do a refresh, etc. compared with how much data will be streaming in during that time.
Not a trivial problem to solve, but can be a fun one if you want to go there.
Oh, and be sure to look to the datasheet for the specific memory part you're using before making any assumptions about what's required of the controller.