Vivado and Hard Macros

[0culus]

So I'm working on a project that uses a Xilinx Spartan-7 FPGA. I need to have a piece of the project be written as a hard macro so that it never changes place and route when instantiated later with other logic. I see lots of resources for writing hard macros in ISE, but it seems Vivado has dumped that feature?

Is there a more idiomatic way to achieve this in Vivado? Perhaps I can export my design as an IP core somehow?

Thanks!

[scatha]

I never used the hard macro feature in ISE but you can do something similar in Vivado using pblocks. The general workflow I've used is:

- Synthesis the design
- Create an appropriately-sized pblock with the EXCLUDE_PLACEMENT and CONTAIN_ROUTING directives set (these stop other parts of the design being placed or routed through the pblock)
- Assign the appropriate cells to the pblock then complete the design implementation
- Once complete, extract the cell placement within the pblock
- Next time you need the block, recreate the pblock and create an identical placement within it (using place_cells) post-synthesis.

Most of this requires tcl scripting. There might be a better way of doing this using the partial reconfiguration workflow, though.

[legacy]

what do you usually do with these macros?

[0culus]

I never used the hard macro feature in ISE but you can do something similar in Vivado using pblocks. The general workflow I've used is:

- Synthesis the design
- Create an appropriately-sized pblock with the EXCLUDE_PLACEMENT and CONTAIN_ROUTING directives set (these stop other parts of the design being placed or routed through the pblock)
- Assign the appropriate cells to the pblock then complete the design implementation
- Once complete, extract the cell placement within the pblock
- Next time you need the block, recreate the pblock and create an identical placement within it (using place_cells) post-synthesis.

Most of this requires tcl scripting. There might be a better way of doing this using the partial reconfiguration workflow, though.

Thanks! I think partial reconfiguration may be locked behind the very expensive paywall...I'm just using the free version. I'll take a look at pblocks.

what do you usually do with these macros?

My understanding is that it is normally used to ensure that a design can be used over and over again while maintaining the same placement and routing. This might be because you had to hand optimize the timing and don't want the tools to dick that up or it's a circuit that's sensitive to changes, and you want it to remain in exactly the same state. My project is the latter.

[legacy]

With ISE I use two UCF files: one for the pinout-mapping & electrical constraints, one for the timing constraints.