It lives on in RISC-V.
Does RISC-V use a lot of MIPSy content, or do you mean spiritually?
RISC-V assembly language is very close to MIPS assembly language. The binary encodings are completely different.
RISC-V rearranged the instruction encoding to:
- provide a huge amount of room for future extensions, even within the standard 32 bit opcode format
- provide uniform support for versions with 32, 64 and 128 bit integer registers
- provide integrated support for optional 16 bit opcodes (like Thumb2) and for 48, 64, 80 ... 192 bit opcodes for future extensions. You can tell the length of an instruction by examining the low-order bits of the first byte: 00/01/10 for 16 bit 00011-11011 for 32 bit, 011111 for 48 bit, 0111111 for 64 bit, nnnXXXXX1111111 for 80+n*16 bit (the XXXXX is for the register to put the instruction result in
All this was achieved, basically, by shortening the field for immediate constants, load/store offsets, and conditional branch offsets from 16 bits to 12 bits. To compensate, the field for LUI and AUIPC is increased from 16 to 20 bits so you can still load any 32 bit constant or refer to anywhere in a 32 bit address space (absolute or PC relative) with two instructions. Unconditional branches also have a 20 bit offset.
The downside is literals and offsets between +/-2k and +/-32k need two instructions instead of one in MIPS. If you use things like the standard "LI" pseudo-instruction then this is transparent.
As well as this, in RISC-V you can compare two registers for EQ/NE/LT/GE and branch in a single instruction (recent MIPS has this too), and load and branch delay slots were removed.
For anyone who knows MIPS it's very very familiar, just improved. And free for anyone to use.
In May, MIPS announced a new 32 bit chip with a new "NanoMIPS" encoding that has 16, 32 and 48 bit opcodes. That looks pretty good too, but it's proprietary as hell and late to the party.