WTF!? Atmega328P vs 2N7002F - fails to turn off!

[KL27x]

NiVagSwerdna, you think the way I do!

There is no code too simple for me to screw up. Any simple change or addition I make to a code, I am surprised if it works on the first try. I spend more time finding my logical errors than writing new code. If my code doesn't work, I am now completely satisfied that it's essentially correct, except for such error I just have to find, lol.

Just last week I fixed an eerily relevant problem where I was calling a subroutine from ISR that was also used in the main code loop, unwittingly sharing a temporary variable between the two. This didn't cause any noticeable problem until over a year later, when I changed some timings on the ISR for an unrelated issue... then a GPIO pin would briefly toggle itself on, on the order of a millisecond, every few seconds.

[NivagSwerdna]

redacted 

[dannyf]

"Just last week I fixed an eerily relevant problem where I was..."

That proves that you are a good human programmer, , because only fools would assume that his code is bug free while debugging it.

The issue at hand is very easy to debug, as the bugs are painfully obvious.

[Kremmen]

"Just last week I fixed an eerily relevant problem where I was..."

That proves that you are a good human programmer, , because only fools would assume that his code is bug free while debugging it.

The issue at hand is very easy to debug, as the bugs are painfully obvious.

The issue at hand turned out to need no debugging as it was a hardware problem.
But by all means do share your pain if you feel like it

[Kremmen]

[...]
SOT23 = TO-236AB   ?! ... naturally.

It is a constant irritation that the same things are multiply standardized - or at least encoded. And the only way to find out is byt exhaustive search because of course there are no comparison sheets or such. At least i never encountered any.

[Kremmen]

I replaced every 2N7002 with Si2308 logic level fets in the problem units and Bob seems to be my uncle. Everything now works without any further changes. Leds turn on and off as expected. Triacs trigger when they are supposed to and everyone is happy.
Note to self: get a reel of Si2308's and delegate the 7002s to other things...

So as far as i am concerned, case closed and thanks for everyone who had constructive comments.

[KL27x]

Glad you fixed the problem!

[Kremmen]

Yeah, whatever. Though i don't really know why you assume i don't understand that hardware needs to be debugged and why you further assume that i have _not_ debugged the problem to the extent needed. Because i have. Turns out it is not a software problem so there.
Hardware problem solved by elimination. Sorry if this is not enough for you but it is enough for me and it is my project.
The only thing i recall mentioning that i haven't gotten to is characterize the 2N7002. It is not high on my list of priorities so i may never get to it what with other things eating my time. If you are not satisfied with that then sorry, but i can live with it.
I am a bit surprised about your belligerent attitude because i fail to see what i did to deserve it. But that is up to you to decide i guess.

[KL27x]

Ooops, I deleted my thread too late. Impulse. Please disregard. Or should I put it back?

My intention is not to ruffle feathers.

i don't really know why you assume i don't understand that hardware needs to be debugged and why you further assume that i have _not_ debugged the problem to the extent needed

I don't assume you don't. But I don't assume you do, either. Why would anyone assume you do, from this thread, alone?

Bob seems to be my uncle.

"Seems" shouldn't have to be in this sentence!

I am a bit surprised about your belligerent attitude because i fail to see what i did to deserve it.

??

My previous post was unfortunately not saved in my clipboard. But as you say, whatever. I'll accept belligerent, as long as the content of the post is also conveyed. Which is to say, if I don't assume anything and go by what you have written, what you have strictly written is slightly lacking in the scientific process. And the conclusion (behavior between 0 and 40mV) so very curious as to merit a more bulletproof verification, maybe. The datasheet suggests the difference there should be between that of jack and @#$#, and jack left town. (Army of Darkness!)

40mV is a perfectly acceptable CMOS digital low output. The output FETs of the CMOS micro pins have a significant RDS, themselves. (What load do you have on there that might be pulling the pin up to 43mV? Who knows? I thought it was just the FET on this pin, which is only capacitive?) Any rate, a logic level FET that changes RDS from megaohms to kiloohms between 0 and 40mV Vgs is a curiosity. At below standardized CMOS logic low, this thing acts like a 50K resistor.

Perhaps you have done a sufficient proof, already, but you did not write it. Perhaps you know you didn't do this, and you don't care. Either way that would be fine. I am posting this because you came back to declare the proof is done... it "seems," without an explanation beyond, "I swapped these crappy FETs with these good FETs and my circuit is now working as I intended. The 2n7002 is crappy. And the problem was not my code."

Extraordinary claims require extraordinary verification. I'm not the only one thinking it. I'm just the idiot with no filter. I'm ordering some resistors from Mouser, and what do you think the chances of me replicating your results are going to be if I add 2n7002 NFET to my cart?

[dannyf]

I tried a few 2n7000: at about 1v, the current goes below 0.1ua, fairly consistently.

[KL27x]

Besides that, I just googled CMOS output voltage levels, and I had to correct my previous post. The max is apparently defined at 50mV, which is a surprise to me and puts a new twist on this. At first, I didn't think anything of 43mV. 43mV is small. But compared to 50mV max, it is a lot.

If his output pin is low, and it's only connected to a FET gate, then should it even measure 43mV? CMOS output is through a FET, itself, which is a purely resistive voltage drop. And with no load, would it even be that high? Where is this 43mV of drop coming from?

So if an output pin is rated for 25mA, let's say, it has to be able to sink 25mA and still maintain 0.05V, max. At a microamp (to cover gate leakage, lol), it should be much less. At 43mV, if the Atmega actually meets spec, this suggests the pin is sinking at least (if not more than) 4/5th of its max output rating simply holding a signal FET gate down. (Or that his pin maybe isn't doing exactly what he thinks it is. Which sounds more plausible?)

So I have a PIC project already wired up on my bench. And I just measured voltage on a PIC output pin digital low with no load. Supply voltage 5V. Pin measures 0.000V. Nada. (And of course I also verified it gives ~5V when the pin goes high to validate my test setup!)

For giggles, if that 43mV were coming from an intermittent high output or an internal pullup resistor, 0.043V/5V is a duty cycle of 0.86% at 5V (or 1.3% at 3.3V), if I'm not mistaken. Enough to give an LED a decent glow. Due to the capacitance of the gate and the rise/fall times of the pin output FETs, the actual duty cycle of the pin might be considerably smaller than 1%, if the frequency is high. This is a situation that might occur... if the ISR is using that pin, for instance. A UART ISR, for example. Just one possibility to consider.

[Kremmen]

Ooops, I deleted my thread too late. Impulse. Please disregard. Or should I put it back?

My intention is not to ruffle feathers.

OK, i will so assume then.

My previous post was unfortunately not saved in my clipboard. But as you say, whatever. I'll accept belligerent, as long as the content of the post is also conveyed. Which is to say, if I don't assume anything and go by what you have written, what you have strictly written is slightly lacking in the scientific process. And the conclusion (behavior between 0 and 40mV) so very curious as to merit a more bulletproof verification, maybe. The datasheet suggests the difference there should be between that of jack and @#$#, and jack left town. (Army of Darkness!)

Well, i wasn't aiming for scientific, i was aiming for fixed. Now it is fixed. But why not, we can continue the study to do the science part as well. Only it has to wait until i make delivery which is the priority here.

40mV is a perfectly acceptable CMOS digital low output. The output FETs of the CMOS micro pins have a significant RDS, themselves. (What load do you have on there that might be pulling the pin up to 43mV? Who knows? I thought it was just the FET on this pin, which is only capacitive?) Any rate, a logic level FET that changes RDS from megaohms to kiloohms between 0 and 40mV Vgs is a curiosity. At below standardized CMOS logic low, this thing acts like a 50K resistor.

In all cases the GPIO pin load is only the fet gate. Nothing else.

Perhaps you have done a sufficient proof, already, but you did not write it. Perhaps you know you didn't do this, and you don't care. Either way that would be fine. I am posting this because you came back to declare the proof is done... it "seems," without an explanation beyond, "I swapped these crappy FETs with these good FETs and my circuit is now working as I intended. The 2n7002 is crappy. And the problem was not my code."

Sorry about being imprecise. I did not mean proof in any math or scientific sense. Rather in the British "proof of the pudding is in the eating" sense. Also, around these parts there is another saying: "if the terrain and the map disagree, the terrain is right". So for me the proof was in replacing a suspect component and seeing the problem go away. After that we can start the science part.

Extraordinary claims require extraordinary verification. I'm not the only one thinking it. I'm just the idiot with no filter. I'm ordering some resistors from Mouser, and what do you think the chances of me replicating your results are going to be if I add 2n7002 NFET to my cart?

Fair enough. You only have to ask nicely and i'll do anything. So, a promise from my part: during the weekend i'll find time to characterize the 3 fets; 2N7002, BS170 and Si2308. Unfortunately i don't have the specific original fets available as those were mutilated during removal. But i do have a lot of them from the same tape reel i.e. most likely the same mfg batch. I'll use thiose and take it on faith that they behave the same.

[Kremmen]

Besides that, I just googled CMOS output voltage levels, and I had to correct my previous post. The max is apparently defined at 50mV, which is a surprise to me and puts a new twist on this. At first, I didn't think anything of 43mV. 43mV is small. But compared to 50mV max, it is a lot.

If his output pin is low, and it's only connected to a FET gate, then should it even measure 43mV? CMOS output is through a FET, itself, which is a purely resistive voltage drop. And with no load, would it even be that high? Where is this 43mV of drop coming from?

The GPIO pins have more electronics than just a simple fet totem pole connected to them. But of course nowhere is a detailed schematic available [edit: <-- which makes it hard to say what the voltage should be in the first place]. Atmel data sheet specifies DC electrical characteristics as Vol@5Vcc as 0.9V max @85C. So 43 mV is way below stated maximum permissible. 2N7002 data indicates that the fet starts conducting somewhere just below 2V (NXP data sheet) or somewhat over 2V (Fairchild data sheet).

So if an output pin is rated for 25mA, let's say, it has to be able to sink 25mA and still maintain 0.05V, max. At a microamp (to cover gate leakage, lol), it should be much less. At 43mV, if the Atmega actually meets spec, this suggests the pin is sinking at least (if not more than) 4/5th of its max output rating simply holding a signal FET gate down. (Or that his pin maybe isn't doing exactly what he thinks it is. Which sounds more plausible?)

So I have a PIC project already wired up on my bench. And I just measured voltage on a PIC output pin digital low with no load. Supply voltage 5V. Pin measures 0.000V. Nada. (And of course I also verified it gives ~5V when the pin goes high to validate my test setup!)

For giggles, if that 43mV were coming from an intermittent high output or an internal pullup resistor, 0.043V/5V is a duty cycle of 0.86% at 5V (or 1.3% at 3.3V), if I'm not mistaken. Enough to give an LED a decent glow. Due to the capacitance of the gate and the rise/fall times of the pin output FETs, the actual duty cycle of the pin might be considerably smaller than 1%, if the frequency is high. This is a situation that might occur... if the ISR is using that pin, for instance. A UART ISR, for example. Just one possibility to consider.

At least Atmel makes no promises that the pin would go anywhere really close to 0 voltage. And that should not be necessary either because typically logic low level is specified somewhere between .5 to 1V depending on the family. So at ~43mV that part should be quite OK. As it is for the other fets, just not for 7002.

[KL27x]

The GPIO pins have more electronics than just a simple fet totem pole connected to them.

Sure they do. But they ALSO have two FETs, source on the rails and drains on the pin. And when they're on, all other sources of voltage drop could/should be bypassed. Such as with my PIC output pin.

Atmel data sheet specifies DC electrical characteristics as Vol@5Vcc as 0.9V max

Ok, this sounds more like what I envisioned, practically speaking. But it's still no matter. The 50mV max spec just opened my eyes to what I initially dealt with as a red herring (because there was already the obvious evidence there that suggested what was really going on). It doesn't matter how high RDSon of the output pin NFET is, because zero current flow = zero voltage drop. So 43mV represents voltage drop which is consistent with just 4.7% (rather than 80+%) of the max output current. So what? This is still 1.2 mA (if your output pin is rated for 25mA), which is still way too high for gate leakage, by about 10^6.

It is easily determined if you have a signal on the pin if you do the diode test I suggested with a faulty board.

It is easily determined what your unloaded GPIO outputs should be expected to measure by testing another one of them that isn't by default a TX/RX pin. Or go all the way and switch the pin in your circuit, as Nivagswerdna had suggested.

It would easily be determined if your FETs are as strange as you think, if you wired one up to a potentiometer on the gate with the same LED. And I wonder if you will see any glow at 50mV Vgs?

Some of these things you can test in less than 60 seconds. You could squash my theory in no time. Yet you continue to pontificate. Perhaps you already did some of these things? Or perhaps you have shrugged off some quirk you have already noticed which is suggestive. Perhaps you still hold out hope that there is an alternate explanation where I am wrong? Do you hate me this much? Or is your hole too deep? You can put down the shovel.

I'm going to predict that the other two FETs you used which "work" do so because their gate capacitance is significantly bigger. They spend less time above threshold, or maybe none at all, as a result, despite the average voltage being unchanged. I have not looked at their datasheets, so it will be curious to see if this isn't the case.

[Kremmen]

Some of these things you can test in less than 60 seconds. You could squash my theory in no time. Yet you continue to pontificate. Perhaps you already did some of these things? Or perhaps you have shrugged off some quirk you have already noticed which is suggestive. Perhaps you still hold out hope that there is an alternate explanation where I am wrong? Do you hate me this much?

Sorry, i do not consider myself to be in a debate with you. I'd say the pontification happens on your side because for me the priority is in the practical fix which is now achieved.
Hate you? I have no feelings toward you either way. You appear a bit quick to take offense but that matters not at all to me as long as this thread stays reasonably civil. If not, i'll just walk.

On the actual subject; the practical issue is that i have a delivery to make. All hardware related to that is already fixed (as in not changeable) - PCBs have been mfg'd and so on. So it is useless to suggest changes there as that won't happen.

I am free to work the circuit in the lab as much as i please but that will take place afterwards, once the stuff is delivered. Once again i say the original issue was not primarily a research project but a purely practical problem. No extra points for thorough dissemination, only for making it work. Now it works so i can move on to other things. I also remind that i am not the forum lab assistant so just hold the comments of me not doing this or that on command.

I have relatively little interest in various hypotheses why this or why that related to this case. Probability suggests that none of the components were actually broken and that they behave as they normally do. I am prepared to verify this somewhat using known good specimens but that's about it. There is nothing any one of us can do to change the components in any way and i won't bother creating workarounds for such an essentially trivial issue. Change a component to something that works, make a note to self and move on.

[KL27x]

delete

[KL27x]

Ok, then. Good night.

For anyone who actually cares:
Si2308  Tgc  6nC
2N7002 Tgc  223 pF
BS170   Tgc  ? on the first datsheet I pulled.  But current capability 2.5x higher suggests higher gate charge.

[dannyf]

For giggles, if that 43mV were coming from an intermittent high output

A plausible explanation - a very low duty cycle output + isolation resistor + gate capacitance means that it can turn on an led briefly if the gate capacitance is low but unable to turn on the led if the gate capacitance is high.

You could squash my theory in no time.

Agreed. debugging this thing is no brainer.

[dannyf]

A 2n7002 reached 0.1ua at 1.34v Vgs.

So unless knockoff parts are at play here, this is not a DC problem.

[KL27x]

I don't know all that much about the silicon. But I would not even attribute this to a "poorly made knockoff." I would consider this FET to be possibly valuable for research. I am certainly going to dig around on the matter before I shrug and toss FETs into bin to "delegate to other things." It might be valuable info to the manufacturer. Perhaps it would even be a scientific lottery ticket of sorts. It might be what puts your name down in history.

I'd certainly want to scope it. Is full saturation at the regular level? Is this huge switching region starting sub decivolt somewhat linear? This could be useful for a variety of things, I can imagine.

Again, I have no clue about the actual silicon, but inherently it seems to be improbable that anything interesting can happen very much below the VFD of a diode junction? Nominally approaching ~0.3V, at least (for a germanium FET?), before anything good starts to happen? This is why I said if OP is really seeing this, he doesn't have a problem, but instead something very interesting!

I was so confident because of my shallow understanding of how FETs work, not because of my shallow experience with embedded programming. Not because I had a similar problem a week earlier, and now I see every problem as ISR. Maybe someone will show how I am wrong, but I think it would be highly unlikely for a FET to behave this way. The rest of the proof, calculating impossibility of current in output pin and demonstrating duty cycle is extra tooth pulling to show what I already believed should be obvious?

A plausible explanation

So far as I can tell, this is the only plausible explanation since the start, for which I am genuinely surprised I didn't get an immediate "duh, thanks, of course, it's so obvious " 2 pages back.

*Edit... ohhh, check my post count.

[NivagSwerdna]

this is not a DC problem.

Would be interesting to see a trace of gate voltage in steady state and in 0->1 and 1->0 transitions

[KL27x]

It would be my prediction that nothing your equipment can measure will happen until Vgs is at least above 0.5V, just like any other silicon FET.

To think a FET turns on at 40mV is similar to believing a red LED will glow at 100mV. This is why I said OP was chasing unicorns. If I can catch one of these, it will be my only project until I figure out how it will make me rich.

0.1ua at 1.34v Vgs.

I am not sure how you are measuring this. But I have imagined you could even just do ohm test with a DMM. I think it would be valid, red probe on drain and black probe on ground/source. It would be testing at VDS of ~3V, or w/e your DMM puts out for its resistance check. Perhaps this could extend your measurable test range.

[dannyf]

To think a FET turns on at 40mV is similar to believing a red LED will glow at 100mV.

Possible with depletion fets - fairly rare for mosfets.

I am not sure how you are measuring this.

using the current range, under 5V supply. So Vds is very close to 5v.

[KL27x]

Oh, ok. I had to google depletion mode. It looks like it would be the same thing in opposite. I mean, 43 mV would for sure completely leave it on, but you would start getting into the grey area at negative voltage between 0 and threshold. 

It has been years since I tried to understand how a FET works, and now that I have just looked at basic information, I don't see where the body diode comes into play, at all, so my own reasoning is possibly completely off, and I got lucky in this instance. The only super basic (i.e. which I can understand, anyway) theoretical information I find suggests that gate charge and resistance are proportional in some way, but it of course doesn't explain the scaling and/or limits. The knee or tipping point, where thing start to happen fast, is still blank in my own understanding. I can guess there's a discrete distance factor between the dielectric barrier/charges across the gate that requires certain minimum force/charge in order to even reach across. And then things would be progress exponentially after that, as the field is perhaps roughly spherical.

The other thing I'm left with is my gut. I think we should have and be using such devices, if they could be made.

So I'm left curious if this FET behavior, RDS of Megaohms to kilo ohms between Vgs of 0 and 43mV is actually as unlikely as I believe. Practically, of course is different. But in theory I have yet to see any reason it could simply not be.

If your lab psu goes down to only 0.1uA, it looks like you can't get close enough to 40mV range to see what's happening, there. I suppose a DMM resistance test wouldn't be any better. At 10Mohm measuring limit, I suppose you end up with the same order of units... about down to a tenth of a uA range, if I am doing the math correctly.

[KL27x]

Oh, lookie. So it's definitely possible:

http://electronicdesign.com/analog/zero-threshold-fet-devices-run-unbiased-consume-microwatts

At least one way is to combine an enhancement mode with a depletion mode FET. That's technically two FETs, but it is still shedding a little more light.

The second sentence of the article also suggests that a regular FET doesn't go below 0.7V (which just happens to be drop of a silicon diode junction.... I have long suspected this could be more than a coincidence, but I have never made a rational connection).