How do PIC32 ISR / Interrupts work?

[741]

Hi,

I'm new to PIC32. I'm trying to understand how the ISR process works, and how one can use the PIC32 scheme effectively.

This is how I currently see things -

Ignoring sub-priorites and natural priorities for now - It looks like that there are 2 places where interrupt priorities 'meet' - First the IPCx registers, external to the CPU core, can be configured to any level up to 7.
When an event occurs, the ISR 'vector' (address) is jumped to. The ISR code itself sets up what priority it operates at via IPLx.

If the IPCx priority is level 3 then the ISR code can in principle set IPL to 2 or lower - but that would be diastarous as then the same interrupt will keep firing the ISR.

So in practice it is common to set IPLx to the same value as IPCx [IPLx = IPCx] - but it could be the ISR sets IPLx to a higher priority [IPLx > IPCx]  - not sure why this would be useful though.

[TomS_]

Not 100% sure what the question is, but have you seen Section 8 of the Family Reference Manual? This covers interrupt processing.

[741]

Yes - I had a look at section 8. However I am not sure I understood it properly, hence this post.

My questions:

• Is my description correct as far as it goes?
• What is an example of where it is useful that the ISR sets IPLx to a higher priority than IPCx?

The new feature for me - if my understanding is correct - is that the ISR can dynamically select its interrupt level.

It looks like, for example, an ISR does not necessarily get serviced "at" the same priority as the hardware interrupt.

I think that for 8 or 16 bit PIC, the only way for an ISR never to be  (itself) interrupted is either
(a) If there are priorities
(b) If priorities are used, and if the ISR is not at maximum priority - disable all interrupts (GIE=0) when the ISR starts

It looks like the PIC32 offers a more sophisticated mechanism - I can choose the priority at which my ISR works?