You CAN NOT wave any of those away as a mere documentation convention, the bit ordering is baked into the hardware -- all the more so with the M88k when you can compute the width:offset pair at runtime.
I know of similar bit-level "unpack" and "pack" instructions in other ISAs, yes.
In my opinion, such instructions are
not enough of a reason to claim bit labeling is somehow subordinate or tied to bit order. Even if the hardware labels the bits in a specific order, you can document the assembly mnemonic and the parameter values using a different labeling method. For example, bit \$b\$ in "least significant bit is bit zero" is bit \$2^{N-b-1}\$ in "most significant bit is bit zero in an \$N\$-bit unsigned integer". You can say it doesn't look nice, but
it is equivalent: the same bits will be affected either way.
It is not like the binary instruction encoding has to reflect the logical definition of the instruction, is it? At least I know of several ISAs where many instructions do not.
So, I
DO still claim that bit labeling is not inherently coupled to bit order or byte order, even if some architectures do so implicitly. And I do still claim that you can change the bit labeling, although you do need to also redefine the documentation for at least the machine instructions (assembly mnemonics) relying on a specific bit labeling.
For example, many ISAs have instructions for counting leading and trailing zero bits. Instead of describing
clz and
ctz as such, you could describe them as
count most significant zero bits and
count least significant zero bits (these definitions applying regardless of what bit labeling scheme one uses, although which is which depends on how the ISA mnemonic names were chosen), and only mentioning as a side note that the actual mnemonic comes from a specific bit labeling scheme. Similarly for any bit-slicing/offset:width instruction encodings, even if the values involve two subtractions.