(Yet Another) DIY Multislope ADC

[NNNI]

Hello!
This is my very first post here, and I think I have good reasons to be nervous - I've come back to the EEVBlog forums many times, since a lot of people have posted their multislope ADC designs here, and for some reason I feel mine is a little...simple. And there is also the fact that I don't own a DMM capable of measuring more than 3.5 digits.

With that being said, here is the story behind and the details of my multislope ADC.

I got started on this project because I got jealous of someone getting a Keithley DMM, so I said to myself: "I'm going to make my own!" Of course, I was only this confident because I'd read the Art of Electronics 3rd edition and knew there was something about similar high resolution DMMs. At first I wanted to make a delta-sigma ADC, but after trying to understand the maths behind it, I decided to try something simpler - namely a dual slope. I got as far as a simulation (https://tinyurl.com/ygr27pba) and making a perfboard prototype, but that didn't work so well and I'd moved on to a multislope, which was described in some detail.

I call the topology I came up with "free-running", because as long as a clock signal is present, the multislope keeps running. Here is a link to a simple simulation:  https://tinyurl.com/yes5kj7v

Surprisingly I got the thing to work on a breadboard, but of course, didn't make any measurements then because I knew it was pointless. I got a PCB made and I was able to make some first-order measurements, but was not able to get the residue measuring ADC working, and that had to be abandoned in favour of the second revision of the PCB, this time with much better parts and an LM399 voltage reference. The uC I ended up choosing was the Raspberry Pi Pico, since I got rather enamoured with it and the 500ksps 12-bit (yes, I'm aware of the quirks, I've read Mark Omo's website about it) ADC it has. Of course, there is a separate 3.3V reference for the ADC, I'm not relying on the noisy internal switcher. As for the actual software, a friend of mine is writing the code for me, and he had a brainwave - using the SPI protocol to provide a clock signal to the multislope, and reading the output of the D flip-flop on the falling edge of the clock signal to get the counts for which the negative reference was turned on, and with some maths you can figure out the time the positive reference was turned on and ultimately the input voltage. This approach worked, as seen in a video I made about it (the second half: https://www.youtube.com/watch?v=ucJOKAhCHTQ, and yep, that's my channel) and I hope with some calibration and residue measurement the readings will start to make sense. No way to test beyond 3.5 digits however...

I'm well aware of the limitations of my topology, especially the fact that each switch is turned on an unknown number of times for a given number of clock cycles, for that reason the PCB has a few jumpers to change the switch inputs to PWM, so I can implement some kind of constant switch cycles algorithm.

I have not been able to test the second revision of the PCB yet, since I've had some trouble finding the LT5400-1 resistor network, but I should be getting some soon and I'll post updates then!

In the meanwhile, here is the schematic and a picture of the board.

[RoGeorge]

Congrats, the board looks very nice!   

[Kleinstein]

If you have trouble getting LT5400:  AFAIK the MORN networks have a compatible pinout, though no thermal pad at the bottom. For the not so high target, this should be well good enough.  The MORN networks may also be available with more resistor values (e.g. 20 K , 50 K).
The resistor R4,5,6,7 are nearly as important for the accuracy.

Just in case you plan the build / polulate another board. The OPA2197 is not the very best choice.  For the reference amplification part I would prefer an OPA2202 (less drift and LF noise).  For the Integrator it is OK though an OPA1642 would be lower noise. There is some advantage to have 2 separate OP for the integrator, so the ouput dirver does not effect the other OP that is setting the precision.

The feedback with the Flipflop makes this a very basic sigma delta ADC.
I may be worth looking at the old solartron DMMs / mark space ADC (e.g. US3918050): when adding a forcing signal one could get a fixed (and lower) switching frequency. The result could still be from the comparator timing directly.

[NNNI]

Congrats, the board looks very nice!   

Thanks, hope it works as well as it looks!

[NNNI]

If you have trouble getting LT5400:  AFAIK the MORN networks have a compatible pinout, though no thermal pad at the bottom. For the not so high target, this should be well good enough.  The MORN networks may also be available with more resistor values (e.g. 20 K , 50 K).
The resistor R4,5,6,7 are nearly as important for the accuracy.

Just in case you plan the build / polulate another board. The OPA2197 is not the very best choice.  For the reference amplification part I would prefer an OPA2202 (less drift and LF noise).  For the Integrator it is OK though an OPA1642 would be lower noise. There is some advantage to have 2 separate OP for the integrator, so the ouput dirver does not effect the other OP that is setting the precision.

The feedback with the Flipflop makes this a very basic sigma delta ADC.
I may be worth looking at the old solartron DMMs / mark space ADC (e.g. US3918050): when adding a forcing signal one could get a fixed (and lower) switching frequency. The result could still be from the comparator timing directly.

Thanks for the suggestions!

I just took a look at the MORN networks and they are indeed cheaper than the LT5400 series, but Vishay does not seem to have them in stock as well. I tried to get some good +/-25ppm resistors for R4 - R7, but they were out of stock, so I think in the next revision I'll end up using more of the MORN/LT5400 resistor networks.

My op-amp choices were dictated by what LCSC had in stock, since I got this board JLC assembled. I'll definitely consider using separate op-amps for the integrators, I can see how having two separate ones will help.

I will definitely take a look at the Solartrons and the mark space ADC.

Thanks once again for the suggestions!

Attached below is the table I made for selecting op-amps, there was another column for slew rate based on which I chose the OPA2197/OPA197.

[Kleinstein]

The choice at JCL is indeed a bit limited. At least they have the OP07 even as a standard part, which is a perfectly fine choice for the reference amplification.  Building an MS-ADC from the parts available at JCL would be a challange - though not impossible.

For the integrator the choice of OPs depends on the intendent integration time. With a relatively short integration (e.g. 20 ms) and switching between the signal and zero input even an TL072 is possible (I had this on the breadboard and still got to the 6 digit range). If a longer (e.g. > 200 ms) integration at a piece is planed / needed to get sufficient resolution (e.g. with the mark space like design) the low frequency noise would become an issue. Than a zero dift OP could be the better choice for the presicion setting OP at the integrator. This OP can use a lower (e.g. +-2 V) supply - there are than quite a few to choose from and a few even at JCL. An AZ OP may want an extra local feedback cap and input resistor. The output driving OP only needs to be fast ( e.g. > 5 MHz GBW would be nice, 10 MHz is good), but the noise hardly matters.
The slew rate is not important, as the OPs are used in the small signal range. A good OP (fast and precision) as a single OP integrator may also work if the reference resistors are equal.

If not limited to the footprint there are other resistor networks that could be used: e.g.  NOMCT (lower noise than NOMCA) and in the low cost corner also the ACAS series.  For the reference voltage there is no need to go for exactly 10 V. A gain of 1.5 or 1.33 would be OK too. For simplicity I used a gain of 2 in my design, though this needs a higher supply.  Using equal resistors and 2 or 3 in parallel / series can be an option, even with discrete resistors.
With reistors from the same reel, 25 ppm/K types may be good enough for the start, as the matching is often quite a bit better than absolute TC. One also usually only cares about a smaller temperature range.

[ali_asadzadeh]

Shouldn't you Connect the 4053 part to +-12V supply!? it's power is only 3.3V and GND.

[Kleinstein]

The 4053 swich does not need a higher supply. The switch directs the currents from the input or the references to either ground or the virtual ground at the integrator input. So the switch pins will see a votlage very close to ground (e.g. +-20 mV around ground). Even if things go wrong with the integrator feedback and the integrator input is no longer at ground, the current from the references and the input is limited by the resistors to a low level (e.g. 100 µA range).

The LV4053 needs the low supply to work with the logic levels too. 5 V supply would help the switches a little (lower resistance), but it than is boarderline with 3.3 V logic levels.

[NNNI]

ali_asadzadeh: What Kleinstein says is right - the switch nodes are more or less at 0V because of the integrator summing junction and the normally closed part of the switch being at ground - this is a current switched topology, and I can get away with powering the 4053 with 3.3V. I could have chosen a higher voltage, but since the 4053 does not have logic level translation for the inputs, and my microcontroller and logic runs at 3.3V.

Kleinstein: True, I've seen the OP07s used in the Solartron 7081 for the same purpose in one of Marco Reps' videos. It is a good op-amp, but there are better ones available, and for the sake of convenience I wanted to use the same op-amp type across the entire board - preferably a single and dual version of the same op-amp, hence OPAx197.

I did use the TL072 in the prototype, but I felt I could do better in terms of noise with a better op-amp choice. I'm not entirely sure about using auto-zero op-amps in the integrator, since I think only stability of offset/bias with temperature is more critical than having no offset. The multislope clock is 100kHz to 125kHz, so run-up should be in the order of 10s or 100s of ms. Maybe a faster clock would have benefitted, or some kind of amplifier at the integrator output, as I've seen on some designs.

Luckily I was able to get my hands on some LT5400-1s, I should be getting them soon and posting the first results here.

[Kleinstein]

The refrence amplifier part is DC only. At DC / very low frequency the OP07 is supperior to the OPA197. In other places the OPA197 can be better.
The right OP for the job depends on the function.

The lower frequency end relavant for the integrator depends on the integration time. With 20 ms or 200 ms integration and thus a relevant frequency of 25 or 2.5 Hz  the OPA197 is still good and no need for an AZ OP. If you "only" want 6 digit resolution the OPA197 would even be OK for 2 seconds integration. With longer integration I would prefer the AZ OP. This requires 2 separate OPs obviously.

The needed intgration time to reach a given resolution depends on the resolution one gets in measuring the charge at the start and end.

The shown hardware seems to have 2 possible methods:
1) the comparator and the timing of zero crossing, like the solatron meters
2) the µC internal ADC to measure the voltage at the integrator, like the HP34401

For comparator method it is about timing resolution. The frequency of the modulation does not directly effect the resoluton. With some 100 ns timing resolution and 100 ms integration time one would be close to 6 digit resolution. It is still a bit less because there are 2 measurements and the references are stronger than the full scale input. So it would need more like 200-500 ms integration to get 6 digit resolution from the pure quantization limit.
The modulation frequency and thus the capacitor size effects the noise for the charge measurement. A smaller cap makes the comparator less critical as the slope is steeper. The extra amplifier (slope amplifier - quite often an NE5534 with 2 additional diodes in the feedback) after the integrator is there to help the comparator. It gives a first amplification stage with a known low noise and allows the comparator to switch faster.  Another, less obvious function of the slope amplifier is to get a defined and not too large bandwidth.  So there is sometimes an extra cap to slow down the slope amplifier, but usually just GBW divided by the gain is enough.

For the ADC way, the modulation frequency makes a difference, as with fast modulation the capacitor can be smaller and this more charge resoultion from the given voltage resolution. However a faster modulation also needs a faster ADC and more critical timing. A crude approximation for the  resolution is the auxiliary ADC steps times number of modulation periods divided by about 3.  For the start I would still not make the speed very high  - first get it working at all (less critical timing) and than think about optimization.

p.s.:
 I just has a look at the ciruit:  ideally one of the currently unused (grounded) inputs of the MUX should also get the raw 7 V reference as an optional input. This the more stable signal than the +-10 V to check the ADC gain.

[NNNI]

I thought that since the OP07 is an old part I might replace it with something new, but I'll take a look at the specifications of both again and maybe change it in the next version.

And yes, this is meant to resolve voltages only down to 1uV (hopefully with the same accuracy) so I don't think I need anything very fancy.

I did leave a lot of options open in terms of selecting run-down/residue measurement. For now, I want to do residue measurement since it does not need exceptional timing. The comparator and the analog switches can be operated by the microcontroller directly - what I was thinking was to try PWM, where the microcontroller outputs PWM in such a way as to have the positive and negative reference switch a constant number of times, and maybe use the comparator output to trigger an interrupt to update the duty cycle in such a way as to keep the integrator from saturating.

I did coincidentally take a look at the famous 1989 HP Journal with the article about the 3548A ADC, and noticed the amplifier before the comparator, but since I'm doing residue measurement I don't need it...for now.

Also the reference voltage is connected to one of the inputs of the MUX, the node is labelled 'RAW'.

Edit: I took a look at the datasheets of the OP07 and the OPA197, and yes, only the OP07 (specifically the AD one) specifies long term stability, so that is definitely something to consider. Thanks for the suggestion!

[iMo]

Double-check whether the OP07 gives you +/-10V output with +/-12V power.
The TI's OP07 DS shows 0.5uV/K and 0.4uV/month.
Would not be an OPA277 better one (0.1uV/K and 0.2uV/month), even we talk 399 ??

[Kleinstein]

The are more modern alternatives to the OP07 - the big pluse with the op07 is it't relatively good availability (even a standard part at JLC).
Getting 10 V out with a 12 V supply is very much boarderline - it may help at low current (e.g. add extra resistors to + or - 12 V to provide all the current and maybe a little more).
For a LM399 ref the OP07 is usually good enough. The resistors for the 7 to 10 V and 10 V to -10 V step are more critical.

1 µV resolution is possible, though not easy. It may need some averaging with the OPA197. In the shown circuit the OP in the integrator sees a noise gain of 3 (or 4 with an extra resistor at the input to reduce the effect of the R_on drift). This would result in about 1 µV_rms noise alone from the OPA197 in the integrator and longer integration would not help much, as there is 1/f noise.

1 µV accuracy with a 10 V range is not going to happen so easy. It may be the limit to call known errors to be acceptable, so a kind of good enough limit. However chances are there are some errors that will be larger. There are plenty of small effect that may cause errors in the low ppm range. A point that can cause some error is the nonlinear resistance of the 4053 r_on. This gives a small square law contribution with a positive sign to the ADC. The small resistors are good for low noise, but can increase the INL.

I would consider 100 µV Ok for the start, later maybe 10 µV if things go well. The OPA197 used as input buffer alone may give an error in the 10 µV range.

Using PWM to control the feedback is an OK idea - I also use this in my new version. However I use a timer interrupt to check only the comparator state once per cyle and than a binary modulation only. Using the comparator timing to get more information for a continuous PWM feedbach is possible, but a bit tricky. It may be easier to use the µC internal ADC also for the feedback.

[NNNI]

It's been a while, but I have an exciting update: I finally got some LT5400 resistors, thanks to a certain ExtraSolar!
I'll start working on the multislope again after I finish the current project I have on hand, a fully discrete CC/CV linear supply.

[NNNI]

It took me way longer than it should have, thanks to some problems uploading code to the Pi Pico (turns out that it is not recognized by the computer when powered externally with 5V) and a mistake in the PCB (ironically, the same one I made on the previous iteration of the board), but I finally got it working!
For now, this is the "free-running" mode where the thing just oscillates on its own with the provision of the clock signal, no measurements being made. The next step I have to take is coming up with an algorithm that implements the constant switch transitions in PIO, do the residue measurements using the in-built 12-bit ADC, maybe use timers to sync to 50Hz, and have the main processor do the maths to turn counts into volts.

[NNNI]

After a few days of work, I was able to implement a constant switch cycles algorithm on PIO.

This algorithm comes from Takovsky (familiar name around here...?) - it uses PWM to maintain a constant number of switch transitions in every cycle to make sure charge injection errors can be calibrated out. The PWM duty cycle switches between (in my case) 20% and 80% depending on the state of the integrator. This makes sure that there is always a zero crossing in every PWM cycle. Here is a link to a Falstad simulation where the PWM generator is implemented using some building blocks: https://tinyurl.com/yfhwuvol

The PIO code was implemented by my collaborator Dimin, who is working on the software.

For now, we have this free-running again, the next thing to implement would be generating N PWM cycles and counting how many times each reference was turned on for 80% of the duty cycle, and then converting those counts into volts. The last step would be to add a residue measuring ADC.

[NNNI]

It has been a while since my last post, but I have not been idle.

I did a lot of research about different multislope algorithms, and I'm going to mention two here.

While I was waiting for code ( I outsource coding ), I was wondering what kind of topology I could make using just some simple logic I had on hand, and what I came up with was a bounded integrator topology - the integrator waveform oscillates between a set positive and negative limit. This is accomplished using a JK flip-flop (4027) clocked at an arbitrary frequency - the higher the frequency, the less chances of over/undershoot and more resolution. The limit comparators are hooked up to the J and K inputs in a way that turns on the respective ref switch to keep the integrator within bounds. Here is a link to a Falstad simulation: https://tinyurl.com/y6g6yans
Since the slopes are much longer, the number of transitions per clock cycle is considerably lesser than the other topologies I've tried - depending on the clock, the bounded integrator topology has around one transition every 10+ clock cycles, free running has between one transition every clock cycle or less, while the PWM method has exactly two transitions per clock cycle. I assumed that keeping the number of transitions as low as possible would reduce problems due to charge injection. Transitions per clock is a very loose measure of charge injection.
Of course, this method is not without its problems - for one thing, the overall frequency of the integrator ramps changes with changing input up to 50%...initially this didn't seem like a problem to me until I realized that the measurement time would have to vary if I wanted a fixed number of slopes, that is, the counts per clock changes with changing input voltage. One more glaring issue is dielectric absorption, which has plenty of room to manifest itself with slow slopes, which leads to loss of linearity. I was later informed that I had partially re-invented the Solartron 7081 ADC, except that I didn't have that weird square wave injection circuit. I have attached a few images of this bounded integrator that I built on a breadboard.

Since I felt like I was waiting around too much for code, I explored the possibilities of making the PWM algorithm work using discrete logic ICs, and I did end up making something using an 8:1 mux (HC151, for example), a binary counter (HC193) and a D flip-flop (4013): https://tinyurl.com/y4xps42r
Making the whole thing using logic would be finicky but not difficult - have the microcontroller generate a clock, pulse a pin to start conversion, and read back the output of the counters using PISO shift registers.  Of course, just using microcontrollers would be the easiest way out, but I found this little thought experiment fun, and along the way did a lot of thinking about the way results are derived from the PWM topology.
Going the logic way, each PWM cycle takes up (in my case) 8 clock cycles, so it would be possible to get 8 counts per PWM cycle, that is, one count per clock cycle. but since the first and last part of the PWM waveforms cancel each other out (duty cycle is either 12.5% or 87.5%, so the first 12.5% and the last 12.5% cause charges of the same magnitude but opposite polarity in the integrator, so they cancel out) and the main counting happens in the difference in duty cycle extremes. So ultimately it comes down to one count per PWM cycle, or one count every 8 main clock cycles.

With all this boring theory out of the way, I will focus on getting the code up and running and actually post results.

Found this interesting paper: https://dspace.mit.edu/bitstream/handle/1721.1/84880/868678609-MIT.pdf?sequence=2

[Kleinstein]

The vesion with simple fixed bounds for the upper and lower limit has the problem with a variable frequency. The DA effect is actually not bad, as the slower part of the DA depends on the average voltage in the integrator. So this part would be rather small.

To get closer to the Solartron working one could use time dependen bonds. So that with time the bonds get lower. The exact waveform for the bonds does not matter, so it could be some RC fitlered rectangular waveform or piecewise linear. The only point is to keep the waveform stable, or use a 3rd comparator for the actual zero crossing. With suitable modified bonds one can get a constant frequency for the PWM signal. The difference to the Solartron (mark - space type) ADC is that the forcing waveform is moved to the other side of the comparators.
A week point of such a contineous integrating ADC is the somewhat limited resolution (~ 0.7 * Integration time / timing resolution ) and that the integration time can vary a bit whern the signal and thus the waveform is not stable. For a fixed time one could in theory read the residual charge with an ADC, like in the HP34401. This may also get a little more resolution than just the timing.

With a constant swtiching frequency the charge injection is not the real problem. It would be only variations in the charge injection that matter. There is still more sensitivity to clock jitter when switching is more often.

[NNNI]

Reading residual charge using an ADC is what I was initially planning, and I will experiment with that too, but the only problem with that is that it involves some math and needs to keep track of the timing between the residue measurements. It requires that both the main conversion and the residue reading be converted to volts before they can be added together, but the dual slope rundown described in that paper produces counts that can be directly combined with the main counts, and then converting counts to volts takes place in the last step. Also, the fixed number of bits of rundown is convenient.

[NNNI]

This might be a bit premature, but I got to finish the 3D printed case and the power supply...and the results are terrible - I could have done a much better job. The only reason I'm pushing it is because I might actually have to use this to make (crude) measurements soon.
As for the software, still working on it. Since I'm using PIO, getting the timings is proving to be a challenge. However, I think I might have just the right person to help me.
Hopefully I'll be able to post actual data and statistics soon.

[NNNI]

Finally got the PIO PWM timings right! now the duty cycle is an exact 1/16 and 15/16, with a frequency of 200kHz which keeps the integrator swing to more or less +/-5V over the entire input range.
The second picture presents something more interesting - I was running the multislope for 50 PWM cycles with input disconnected (i.e., corresponding analog switch turned off), and after every 50 cycles the integrator voltage went up by a small bit. I think this is because of charge injection from the 4053 analog switch, so I zoomed out on the scope (second image), and the integrator voltage did increase linearly. The multislope was running for around 250us every 1 second, and at 10 seconds per division you can see how the integrator voltage in yellow goes up a little bit, and the result is a nice and linear ramp. This is good news because it confirms that charge injection effects are indeed linear (at least at this temperature and supply voltage) and can be calibrated out.

[Kleinstein]

With a constant switching frequency the charge injection part is essentially constant and thus easy to subtract. It is just part of the offset.

The slight shift that happens represents the offset of the ADC input and there are multiple contributions to it. The more important are:
Asymmetry in the references (from resistors and OP offset)
Tolerances in the resistors for the +10 V and -10 V ref.
The offset of the "slow" OP at the integrator
leakage currents at the 4053
mismatch in 4053 resistance
input bias at the integrator
net charge injetion
pulses in the residual voltage at the integrator input voltage, that can be slightly asymmetric for the 2 directions

It is a good sign that the drift rate seen is about constant. This gives hope to not have large nonlinear effects depending on the integrator output voltage. There may still be small INL contributions, as for the final result it is about some 100 µV or so ín the integrator voltage after some 20 ms, or some 5 mV after a second.  The time with the integrator in hold mode is naturally not causing much errors.

[NNNI]

It is finally time for the first super-crude results!
So I got the timings right and input sorted out, so just for the hell of it I set the ADC up to do one reading per second, 5000 PWM cycles so 5000 counts with no residue reading. I took 1990 readings over something like half an hour and made a histogram (inspired by https://pico-adc.markomo.me/INL-DNL/), and the results actually looked interesting.
Next, measuring in PLCs and rundown residue.

[NNNI]

Another rather disappointing update.
The first picture (yellow - integrator, blue - positive reference switch, pink - negative reference switch, dark blue - input switch) shows a sample multislope cycle: "Desaturation", which is reading the comparator and setting one of the reference switches so that the integrator goes to zero so it does not start with a random charge. This was a problem that caused noisy results. Second, of course, is PWM - 1/16 and 15/16 duty cycle. Then comes pre-rundown, which adds a constant dummy charge to the integrator to make sure it is negative for the next step - rundown. Rundown involves ramping the integrator up till zero is reached and counting the number of cycles it takes to do so.
Initially, I tried one PLC of measurement followed by one PLC of integrator zero, but added a lot of noise to the result, so I changed to 20PLC worth of continuous integration (200ms).
The results, however, are rather interesting. There is still quite a bit of noise on the ADC, but there also seems to be some kind of bug that causes two "groups" of readings, as shown in the second picture. A count is worth 10uV.
Of course, I do not know what the bug is yet, but given how hastily and poorly designed this ADC is, I want to start fresh with better parts and better PCB layout and better practices in general. It was an interesting experiment and I learnt a lot from it.

[Kleinstein]

The 2 groups of result look indeed like a bug (SW problem). As the noise is quite high even the "noise" could still be a SW problem.

Much of the noise looks like it effects both groups and would thus be rather low frequency noise. The 1/f noise could be a problem and it may be worth considering to alternate between a conversion from the input an one from 0 V and than look at the difference only.

The ADC circuit has a few weak points, but overall it does not look that bad and I would expect better performce should be possible.
I looks a bit like there could be quite some overshoot at the integrator (could as well be the ground hook at the scope probes). A good testpoint for the integrator is the ouput of U6B, so the "slow" OP in the compound integrator. This should give a kind of rectangle signal with some overshoot, but not too much ringing. From my experiences and simulations it may need some resistance (e.g. 100 ohms range) in series to C19 to dampen ringing.

It could be a good idea to have some kind of filtering BW limit between the integrator and comparator. The slope amplifier found in many implementations between the integrator and comparator also has the task to limit the bandwidth.

A weakness in the circuit as shown is that the resistance for the input in twice the resistance for the references. This leads to incomplete compensation of the drift of the switch on resistance. So ideally there should be the same resistance,even of this means a slightly small input range (like +-8 V) only.

For testing it may still help to first look at short integration and possibly even a more dual slope like mode with seperate input and reference integration. This gives less resolution and mode noise, but makes errors more visible.
With only a single slope for the run-down the resolution is quite limited. There are 2 options to add a smaller slope with relatively little effort even to the existing PCB:
1) add a resistor (e.g. 1 M range) from the +7 V ref. to the integrator input. So there would be no more stop mode but slow drift instead. This would be similar to the small slope in the Keithley 2000

2) add a resistor (e.g. 220 K) in parallel to R7 and this make the references a little asymmetric. Than the case with both reference channels actice acts as small slope. This however needs a little more math in looking at the result. This is like my ADC solution works.