12.8 MHz from 10 MHz

[mojoe]

Asking for ideas on ways to generate a 12.8 MHz clock signal that is referenced and/or derived from a 10 MHz OCXO. The 12.8 MHz clock is used in a radio, as a master reference.

I'd like to use what I already have on hand, if possible. I have some 14-pin Micro Crystal 10 MHz OXCO's, some AD9850 and AD9851 modules that I got from ebay some time ago, some IDT ICS501 LOCO PLL multipliers (this chip does x2, x3, x3.125, x4, x5, x5.3125, x6, x6.25, x8, but sadly, nothing binary), various 74xxx chips, various PIC, ATTiny, ATMega, Arduino, and probably other parts I'm forgetting.

The first, obvious solution that occurs to me is to to use the ICS501 to multiply the 10 MHz x3, use that to clock one of the AD9851 modules (replacing the stock 30 MHz oscillator), and use a uC to program the AD9851 to output 12.8 MHz.

However, there is probably some simpler, more elegant way to do this. Since the 12.8 MHz is binary, it occurs to me that perhaps there is some way to do this with logic chips, or a microcontroller, using the 10 MHz OCXO as a reference.

BTW, I did check the datasheets of other LOCO PLL chips, but none seem to have any binary multipliers.

Please offer up your suggestions. I'm sure someone here has a brilliant solution (being very serious).

Thanks.

Edit: fixed type (ISC501)

[edavid]

ICS501 to multiply 10MHz by 8 = 80MHz
74AC163 or similar to divide by 5 = 16MHz
ICS501 to multiply by 4 = 64MHz
74AC163 or similar to divide by 5 = 12.8MHz

(But I would buy a 12.8MHz OCXO instead.)

[cj]

Here are two solutions requiring 12.8MHz VCO or VCXO

1)
Divide 12.8MHz by 32 so you get 400kHz
Divide 10MHz by 25 so you get 400kHz again but duty cycle isn’t exactly 50% but that’s not a problem.
Phase compare both 400kHz signals using 74HC86 gate and feed output of 74HC86 gate via loop filter to 12.8MHz VCO/VCXO.

2)
You could also construct a 0.78125 digital divider by skipping ever fourth cycle seven times but the 8th time you keep the cycle. In this way 7 cycles are removed in a 32 sequence. So you get 25 output cycles for every 32 input cycles. If the input frequency is 12.8MHz the average output frequency is 10MHz.
Compare both 10MHz signals using 74HC86 gate and feed output of 74HC86 gate via loop filter to 12.8MHz VCO/VCXO. Because of the cycle skipping the phase comparator output will have a ripple but that will be filtered out by the loop filter.


CJ

[eblc1388]

This is my idea, out of my imagination.

Construct a oscillator with a 12.8MHz run of the mill crystal, trimming it close to output 12.8MHz using the usual two capacitors.

Use a 8-pin AVR, clocked by the 10MHz OCXO, toggling a output port pin to give 400KHz,  via an infinite software loop with 12 clock cycles HIGH and 13 clock cycles LOW. Or it might works even better with a narrower output pulse.

Force feed this 400KHz signal using a small value capacitor into the 12.8MHz oscillator to synchronize its output to 12.8MHz.

 

[CJay]

A complicated method (I've got one with the Rb and it works quite well as a master reference for a few PMR radios I have):

http://www.mediafire.com/view/0x5sa7o0s9pgc4s/Tait_T801_Frequency_Reference

But:

Maybe try feeding the AD9851 with the 10MHz, use the internal multiplier and build a 5 pole LPF for the output

Calculate tuning word here:

http://www.analog.com/designtools/en/simdds/?part=AD9851&fin=10M&mult=6&ftw=369D036A&rso=111111&harmonicDB=-50&useFilters=1&fType=0&fTop=1&fOrder=5&fc=12.8M&fRipple=0.5

Filter design here or find a copy of Elsie:

http://www.wa4dsy.net/filter/filterdesign.html

[GeorgeOfTheJungle]

You could use this table:

Code: [Select]

m x
(10/x)*m= 12.8 2 => x= 1.5625
(10/x)*m= 12.8 3 => x= 2.34375
(10/x)*m= 12.8 3.125 => x= 2.44140625
(10/x)*m= 12.8 4 => x= 3.125
(10/x)*m= 12.8 5 => x= 3.90625
(10/x)*m= 12.8 5.3125 => x= 4.150390625
(10/x)*m= 12.8 6 => x= 4.6875
(10/x)*m= 12.8 6.25 => x= 4.8828125
(10/x)*m= 12.8 8 => x= 6.25
Choose a divisor (x) for the 10 MHz from the table, divide using the counters of the avr and then multiply (m from the table) with the ISC501. For example, to divide by 6.25 count 6,6,6,7 or 6,7,5,7, etc so that (a+b+c+d)/4 = 6.25.

[edavid]

Force feed this 400KHz signal using a small value capacitor into the 12.8MHz oscillator to synchronize its output to 12.8MHz.

Injection locking produces too much phase noise for a radio reference.

Choose a divisor (x) for the 10 MHz from the table, divide using the counters of the avr and then multiply (m from the table) with the ISC501. For example, to divide by 6.25 count 6,6,6,7 or 6,7,5,7, etc so that (a+b+c+d)/4 = 6.25.

This won't work because of the minimum input frequency of the ICS501 (not ISC501).  You have to multiply first, then divide.

[GeorgeOfTheJungle]

Choose a divisor (x) for the 10 MHz from the table, divide using the counters of the avr and then multiply (m from the table) with the ISC501. For example, to divide by 6.25 count 6,6,6,7 or 6,7,5,7, etc so that (a+b+c+d)/4 = 6.25.

This won't work because of the minimum input frequency of the ICS501 (not ISC501).  You have to multiply first, then divide.

You learn something new every day... 

[fcb]

Silicon Labs excellent little Si5328

https://www.silabs.com/documents/public/data-sheets/Si5328.pdf

[edavid]

Silicon Labs excellent little Si5328

https://www.silabs.com/documents/public/data-sheets/Si5328.pdf

But does it make sense to spend $13 on this IC, when he could buy a 12.8MHz OCXO for $19?

[duak]

Another method to cleanly double a frequency is to use an analog multipiler with the input signal driving both the X & Y inputs.  This takes advantage of the trig identity where sin(wt) x sin(wt) = sin(2wt) where wt is the angular frequency.  Back in the bad old days before the current crop of synthesizer and clock multiplier chips, a colleague used an Analog Devices AD834 to realize a 0 - 30 MHz reference clock driven by an NCO.  The AD834 is about $20 though.

Cheers,

[Kleinstein]

The old days way is to synchronize an 12.8 Mhz oscillator to the 10 MHz clock by adding a small amount of the 10 MHz (or maybe divided to 400 kHz or 2 MHz) to the oscillator.  If close enough to the correct frequency there will be synchronization to exactly the right frequency. Ideally the 12.8 MHz would be a crystal, but an LC oscillator would also work.

[SiliconWizard]

The rational ratio is 32/25 so as edavid suggested, you can multiply by 32 by cascading two ICS501's (x8 then x4), and divide by 25 with a combination of counters you have available.
By inserting a divider between each ICS501 as he suggested instead of multiplying by 32 and then divide, you will keep the max output freq of the ICS501 within specs (160 MHz max).

Of course this is not optimal in terms of part count or power draw, but it should be doable with the parts you have at hand.

I'm afraid any "simpler" solution will require to buy a specific PLL IC and possibly have means of programming it, because it's not at all likely that you'll find one that can be programmed with this specific ratio with just a few pins configuration, so expect either I2C or SPI, which will require some kind of MCU. So may not be that much simpler actually, not that much less power hungry, unless you already have an MCU on board that you could use for this.

Since off-the-shelf fractional-N PLLs tend to be targeted at much higher frequencies nowadays, it may not be easy to even find one that would fit. The Si5328 is one of the few and pretty cool but a bit pricey and would require an additional MCU to be configured with.

So yet another solution that would probably be the most cost-effective for a product (probably not for just one prototype) could be to use a very small FPGA/CPLD that has a built-in PLL and internal Flash. Many do. The downside is, you will have to program it, but it's not very difficult. You can even use it for additional glue logic. Lattice has chips that can be a good fit for this, for instance in the iCE40 series.

[mojoe]

ICS501 to multiply 10MHz by 8 = 80MHz
74AC163 or similar to divide by 5 = 16MHz
ICS501 to multiply by 4 = 64MHz
74AC163 or similar to divide by 5 = 12.8MHz

(But I would buy a 12.8MHz OCXO instead.)

This seems like the easiest solution, using what I have. And no micro needed.

BTW, where do you get a 12.8 MHz OCXO for $19? The only one I find in that price range is on ebay for $28.90 with shipping. His link to the datasheet doesn't work, so I don't know the supply voltage, or what it outputs. Besides, I don't have an ebay account.

The least expensive 5V through-hole part in stock from Mouser is $155.71 w/o shipping.

[mojoe]

Silicon Labs excellent little Si5328

https://www.silabs.com/documents/public/data-sheets/Si5328.pdf

Yes, if I were to order new parts, I was thinking it would be simpler to use one of the Si parts.

[edavid]

BTW, where do you get a 12.8 MHz OCXO for $19? The only one I find in that price range is on ebay for $28.90 with shipping. His link to the datasheet doesn't work, so I don't know the supply voltage, or what it outputs. Besides, I don't have an ebay account.

https://www.ebay.com/itm/NEW-1pcs-C-MAC-STP-2500-LF-12-8MHZ-Crystal-Oscillator-CSL/171746830143

Or how about a TCXO for $20?

https://www.ebay.com/itm/1-USED-TOYOCOM-TCO-903A-12-8-MHz-20x20-0-5PPM-Adjustable-TCXO-Crystal-Oscillator/332386541592

You want a datasheet too?

[bson]

If you double it to 20MHz first you get a 16/25 ratio for 12.8MHz.  (Or 32/25 total.)

[bson]

If it were me I'd use an MSP430G2203, feed it the 10MHz, and set up the internal DCO/PLL to multiply it up to 12.8MHz and output that on a pin.  20 pin SSOP, miniscule power consumption, $.60 in quantity (and maybe a buck qty handful from Mouser/Digikey).

[BrianHG]

I've used this guy with great success:
CDCE925PW
http://www.ti.com/product/cdce925?keyMatch=CDCE925PW&tisearch=Search-EN-Everything

It has 2 PLLs, optional voltage control tuning pin for a crystal if used instead of a fixed clock & flash memory so you may program it once and just let it power up functional in circuit.  And they are cheap at 2$.

[fcb]

Silicon Labs excellent little Si5328

https://www.silabs.com/documents/public/data-sheets/Si5328.pdf

Sure. I don't know enough about the users application to make that call. For example: What if they need to lock the 12.8MHz to the 10MHz coming from an external source?

[edavid]

If it were me I'd use an MSP430G2203, feed it the 10MHz, and set up the internal DCO/PLL to multiply it up to 12.8MHz and output that on a pin.  20 pin SSOP, miniscule power consumption, $.60 in quantity (and maybe a buck qty handful from Mouser/Digikey).

Can you say more about how this works?  The MSP430 documentation seems very confusing.

Is it a PLL or FLL?

[mojoe]

Yes, I'd like to see how to do this with an MSP430 as well.

Edit: I just looked in the parts bin and see that I have some MSP430F2013 and MSP430G2553 on hand.

[BrianHG]

If it were me I'd use an MSP430G2203, feed it the 10MHz, and set up the internal DCO/PLL to multiply it up to 12.8MHz and output that on a pin.  20 pin SSOP, miniscule power consumption, $.60 in quantity (and maybe a buck qty handful from Mouser/Digikey).

Can you say more about how this works?  The MSP430 documentation seems very confusing.

Is it a PLL or FLL?

No, it's a micro controller unit.  You know, get a compiler, write a program, software program it's internal PLL, output that internal clock to a pin.  I wouldn't trust it's output purity and stability compared to a dedicated PLL like the one I mentioned.  The TI unit I mentioned (CDCE925 or cheaper CDCE913) you can type the frequencies you are using and want on each output into TI setup software, and it will program the IC for you, or give you the I2C setup registers.
I've used it for a video graphics clock generator ranging from 180Mhz to 12Mhz with 0.01Mhz steps without any jitter or noise.

[edavid]

Is it a PLL or FLL?

No, it's a micro controller unit.

I realize that, but I was asking if the internal frequency generator was a PLL or FLL.  Most of the documentation says FLL, but I couldn't find details.  Usually an FLL produces too much phase noise to use as a radio LO.

[mojoe]

I just read the docs regarding the CPU clock and DCO. Yes, it looks like it's FLL, not PLL.

[Brumby]

I don't know enough about the users application to make that call. For example: What if they need to lock the 12.8MHz to the 10MHz coming from an external source?

That was the direction of my thinking as a first reaction.  Clarifying if this was the case would be one of the first questions I would be asking.

The answer could change your options drastically.

[German_EE]

Drive one of your DDS modules with the 10 MHz signal and generate 2.8 MHz. You then mix together 10 MHz and 2.8 MHz and feed the result through a 12.8 MHz bandpass filter and amplify.

[AndyC_772]

Cypress CY22393F

[bson]

For some reason I missed that it's for a radio LO - yes, using a uC FLL for that probably would be too noisy.  However, I think you'd find the noise spectrum dominated by 1/w meaning the DCO-FLL doesn't add much high frequency noise as it's more prone to wander, which the FLL counteracts, than jitter, necessarily.  Jitter would be fixed spurs from the FLL stepping, and those might be suppressable.

But that's kind of a back-asswards way of solving it, and there are definitely easier solutions.  (Maybe just build an oscillator with a PLL, no need for a VCO since it's fixed frequency and all you need to do is phase lock it.)

Edit: PLXO circuit design seems to be beyond what's easily found on the net... I guess most just drop in a programmable PLL clock synthesizer and call it a day.

[arduinew]

Hello,
re
"Here are two solutions requiring 12.8MHz VCO or VCXO
1)
Divide 12.8MHz by 32 so you get 400kHz
Divide 10MHz by 25 so you get 400kHz again but duty cycle isn’t exactly 50% but that’s not a problem.
Phase compare both 400kHz signals using 74HC86 gate and feed output of 74HC86 gate via loop filter to 12.8MHz VCO/VCXO. "

I am curious, the thread starter, Mojoe, wanted 12.8MHZ, so how does he divide to 400k what he hasnt got?!
But assuming he can,
could U pls explain the above to me.. why 400kHz? i get that 400k is a divided 12.8, and the 74HC86 Xor function, but how does that help?
Thanks!
Arduinew

[CJay]

Hello,
re
"Here are two solutions requiring 12.8MHz VCO or VCXO
1)
Divide 12.8MHz by 32 so you get 400kHz
Divide 10MHz by 25 so you get 400kHz again but duty cycle isn’t exactly 50% but that’s not a problem.
Phase compare both 400kHz signals using 74HC86 gate and feed output of 74HC86 gate via loop filter to 12.8MHz VCO/VCXO. "

I am curious, the thread starter, Mojoe, wanted 12.8MHZ, so how does he divide to 400k what he hasnt got?!
But assuming he can,
could U pls explain the above to me.. why 400kHz? i get that 400k is a divided 12.8, and the 74HC86 Xor function, but how does that help?
Thanks!
Arduinew

Necro post mate, the original thread is from 2018.

[eblc1388]

"Here are two solutions requiring 12.8MHz VCO or VCXO
1)
Divide 12.8MHz by 32 so you get 400kHz
Divide 10MHz by 25 so you get 400kHz again but duty cycle isn’t exactly 50% but that’s not a problem.
Phase compare both 400kHz signals using 74HC86 gate and feed output of 74HC86 gate via loop filter to 12.8MHz VCO/VCXO. "

I am curious, the thread starter, Mojoe, wanted 12.8MHZ, so how does he divide to 400k what he hasnt got?!

If you re-read the above quote carefully, you'll notice it said "Here are two solutions requiring 12.8MHz VCO or VCXO". The OP will need to build/obtain an 12.8MHz oscillator first, either a VCO or a VCXO for the solution to work.

Getting this oscillator is not the problem, it is making it always generate 12.8MHz with the same accuracy of the reference 10MHz OCXO. The solution is to phase lock it's output to the OCXO's 10MHz output but this can only be done if the two sources share a common frequency. The idea is to divide these frequencies with different divisiors so they end up at the same frequency. It turns out that 400KHz is the common frequency which can be obtained from both 12.8MHz and 10MHz with different divisors of 32 and 25. After such divisions, both 400KHz outputs can be fed to a phase comparator resulting in an error control voltage which can be used to steer the 12.8MHz oscillator back to the target frequency. Now the 12.8MHz is "sync" or "lock" to the 10MHz OCXO and have the same stability. 

A VCXO is a better choice as the frequency change per control voltage would have much finer resolution around the target frequency.

I hope this will answer your question.