Some VHDL for 4 digit 16 bit muxed. Fits in a Lattice LSI1016.
entity hex_decode_16 is
port(
clk: in std_logic;
reset: in std_logic;
hex_in_a: in std_logic_vector ( 3 downto 0 );
hex_in_b: in std_logic_vector ( 3 downto 0 );
hex_in_c: in std_logic_vector ( 3 downto 0 );
hex_in_d: in std_logic_vector ( 3 downto 0 );
seg_a_out: out std_logic;
seg_b_out: out std_logic;
seg_c_out: out std_logic;
seg_d_out: out std_logic;
seg_e_out: out std_logic;
seg_f_out: out std_logic;
seg_g_out: out std_logic;
dig_1_out: out std_logic;
dig_2_out: out std_logic;
dig_3_out: out std_logic;
dig_4_out: out std_logic);
end;
architecture Hex_decode_16 of hex_decode_16 is
signal digit: std_logic_vector(3 downto 0);
signal hex_in: std_logic_vector(3 downto 0);
signal segments: std_logic_vector (6 downto 0);
begin
process (clk, reset, hex_in_a, hex_in_b, hex_in_c, hex_in_d)
begin
if rising_edge(clk) then
if reset = '0' then
digit <= "0001";
else
digit <= digit(2) & digit(1) & digit(0) & digit(3);
end if;
end if;
case digit is
when "0001" => hex_in <= hex_in_a;
when "0010" => hex_in <= hex_in_b;
when "0100" => hex_in <= hex_in_c;
when "1000" => hex_in <= hex_in_d;
when others => hex_in <= "0000";
end case;
case hex_in is
when "0000" => segments <= "1111110";
when "0001" => segments <= "0110000";
when "0010" => segments <= "1101101";
when "0011" => segments <= "1111001";
when "0100" => segments <= "0110011";
when "0101" => segments <= "1011011";
when "0110" => segments <= "1011111";
when "0111" => segments <= "1110000";
when "1000" => segments <= "1111111";
when "1001" => segments <= "1110011";
when "1010" => segments <= "1110111";
when "1011" => segments <= "0011111";
when "1100" => segments <= "1001110";
when "1101" => segments <= "0111101";
when "1110" => segments <= "1001111";
when "1111" => segments <= "1000111";
end case;
(seg_a_out, seg_b_out, seg_c_out, seg_d_out, seg_e_out, seg_f_out, seg_g_out) <= segments;
(dig_4_out, dig_3_out, dig_2_out, dig_1_out) <= digit;
end process;
end Hex_decode_16;
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