The device will add the frequency tuning word to the phase accumulator at a rate of the clock frequency, and then the phase accumulator goes to the lookup table. That's the basic DDS architecture.
With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.
f/fc = 0.126154 - this is the frequency tuning word.
Now add this over and over again, at a rate of 1.3 MHz / 769ns:
0.126154, 769ns
0.252308, 1.538462µs
0.378462, 2.307692µs
0.504615, 3.076923µs
0.630769, 3.846154µs
0.756923, 4.615385µs
0.883077, 5.384615µs
0.009231, 6.153846µs (overflow)
0.135386, 6.923077µs
0.261540, 7.692308µs
0.387694, 8.461538µs
0.513848, 9.230769µs
0.640002, 10µs
0.766156, 10.76923µs
0.892310, 11.53846µs
0.018464, 12.30769µs (overflow)
The frequency is approximately 1/6.153846µs or 162.5 kHz. The next time around it'll be a slight bit different because the overflow didn't occur at exactly an integer step, and the average frequency will work out to 164 kHz (write a script to run this for a large number of periods and calculate the frequency at the end, if you like).
No change in clock, no change in DAC resolution. There are eight steps per period, and you'll notice that the values look similar between the two periods I did, but they're not the same.
Edit: By the way, things start to get "interesting" when the set frequency is a nice integer ratio of the clock. Try it, you will lose a bit of effective resolution. There's a reason ADI's DDS sim gives a nice ugly warning if you set it up that way. But that's nothing to do with the DDS chip, that's math. Even this very basic accumulation will exhibit it.