Hey Bbqstingray,
Thanks for posting the images. A few comments from my side:
Creating split reference (gnd) planes is a tricky job and I would say don't do it unless you have a concrete reason. In this case even in TI's schematic/layout example they just connect the AGND directly to PGND. In reality though you have a full plane on Layer 2 so this isn't really a split.
If you did need to split planes sometime in the future, this is normally done by using separate Gnd symbols in the schematic. These would be connected by an inductor to keep the same DC level but isolate high frequency currents.
The trick comes when you have a signal trace that crosses over this split. You need to consider that this signal carries a current which needs to have a return path through the reference plane. If there is a split or slot in the plane this return current needs to take the long way around, which causes a larger-than-necessary current loop that contributes to electromagnetic radiation or susceptibility.
Your ISNS+ signal on the bottom layer is doing something like that. If you did not have a solid plane on Layer 2 the closes return path would be through Pin2 of the output connector. This would make a small antenna to pick up extra noise for the input of your current sense amplifier (the opposite of what splitting planes is usually expected to do).
A couple of other things I noticed while perusing:
1. Normally the feedback point would be after the output current sense resistor. It is good to also have some of that capacitance after the resistor so that it is less isolated from the load. However since it looks like you are going to have an external output harness this will probably make little difference.
Personally I avoid resistance values above 100k when possible and would scale down the dividers to something lower. It makes the design less sensitive to leakage currents, moisture, etc.
2. The big one for switching regulators: switch loop area. The loop area for the current that travels through the inductor should be minimized to reduce radiated emissions from the design. For example you could modify the orientation of the FETs so the inductor vias can be directly between the high and low sides. Then the inductor could be placed directly underneath the FETs for a more compact layout.
Additionally the excess area for the switch nodes on Layer 1 should be removed. Excess copper on the switch nodes (beyond what is needed for the load current) just adds more parasitic capacitance which causes ringing during switching and more radiated emissions
That got out of hand
, hopefully it points you where you want to go.
Cheers,
Oam