74LVC "additional supply current per pin"?

[ebastler]

In a 74LVC series datasheet, the "static characteristics" on page 5 state the expected low quiescent current of 0.1 µA typical, 4 µA max. But they also specify an "additional supply current" of 5 µA typical, 500 µA max. per pin (!):
https://assets.nexperia.com/documents/data-sheet/74LVC1G04.pdf

I can't find a similar additional current specified in some other modern CMOS families, e.g. here for a MC74VHC gate, see page 4:
https://www.onsemi.com/pdf/datasheet/mc74vhc1g04-d.pdf

Is that LVC additional current real? Is it indeed a static current that the IC draws, as implied by its inclusion in the "static characteristics" section, or am I misunderstanding something?

[ArdWar]

Uh, not really. That is what I call "transition current", the current drawn by input structure when a input pin is not at full HI or LO state.

It is technically static, as it is not strictly switching characteristic. It's just happen that the specific static condition usually happens during switching.

[Kleinstein]

That extra current can be an issue when using the chips for logic level conversions (e.g. 3.3 V signal to 5 V chip or some 2.3 V signal for a 3.3 V supply). It is not just a thing with 74LVC, but most of the CMOS logic, even the 74HCT... , that is kind of made to also work with a smaller input signal.

[ebastler]

Aha, thank you both! The additional current is specified for inputs at Vcc-0.6V, but I assume that it applies for any input voltage which is not (pretty) exactly Vcc or 0V? Is it essentially getting worse the farther the input is away from Vcc or 0V?

[langwadt]

Aha, thank you both! The additional current is specified for inputs at Vcc-0.6V, but I assume that it applies for any input voltage which is not (pretty) exactly Vcc or 0V? Is it essentially getting worse the farther the input is away from Vcc or 0V?

some datasheets have graphs like: fig8/9,  https://assets.nexperia.com/documents/data-sheet/74HC_HCT14.pdf

[ArdWar]

If you're lucky the datasheet may contain a chart on how the input structure behave.
This one shows how HCS family behave. It has Schmitt input, my favorite part to deal with signal of questionable quality.


Unfortunately most datasheets don't include any info at all. So yeah, good luck decoding all those fancy letters and familiarizing with how each family behave. For example "T" devices (as in TTL compatible one) usually have more leeway on the high input signal before it gest ugly.

[Kleinstein]

The graphs are often found for schmidt rigger inputs, because these are also for not so clean signals, like slow rising. Normal logic input can be a bit similar, but usually without the hysteresis.
There is usually no extra current when there is a clean logic signal, like < 25% and > 75% of the supply. How much current and from what voltage level it starts seem to vary between units. Thus the rather large difference between the typical and maximum numbers. The logic chips are usually cheap and thus not tested very well for parameters that most of the time don't matter. If critical in some applications (e.g. use for level shifting in a power sensitive application) it can make sense to check the parts (or at least some from the same batch) upfront.

It is interesting to see the curve for AHCT14 to be really shifted to lower voltages.