ADP7102 low-noise linear regulator, nearby objects produce dc offset at output

[jfedison741]

Hello,
I am testing a low-noise linear regulator, ADP7102ARDZ-5.0-R7, and have found that the output voltage appears to shift when an object is placed near the top of the IC.

For example I am getting about 330 uV of dc voltage shift in the output when I bring the eraser end of a conventional pencil within 2mm of the top of the IC (SOIC-8 package). Large objects near the top of the IC can cause larger dc shift, up to around 5mV.

Vout at Iload=10mA
5.00105V (no object nearby)
5.00072V (eraser end of conventional pencil within 2mm of IC)

Here is the schematic (DaveCAD format):


I have left the exposed thermal pad floating (the regulator is only dissipating 16 mW). Per the datasheet the exposed pad (EPAD) is internally connected to ground.



Anyone have ideas why such dc shift is showing up and how to solve?
Thanks.

[Someone]

Try lights/sun on, and off.

You've probably got some small photoelectric effect, plastic packages don't completely block light.

[mawyatt]

Also might be oscillating, check output with a scope.

Best,

[jfedison741]

Try lights/sun on, and off.

You've probably got some small photoelectric effect, plastic packages don't completely block light.

Thanks for your suggestion -
Tried with and without room lights, has no effect on output voltage. Also tried with and without 60W incandescent up close and no effect.

A clear zip lock bag placed close to the IC causes a very large dc shift:
5.00335V (no bag) to 5.00866 V (bag within 5 mm)

[PeteH]

Is this something related to thermals?
The part is expected to shift quite a bit over line, load and temperature.

Are you concerned with hundreds of microvolts of DC shift?

[jfedison741]

Also might be oscillating, check output with a scope.

Best,

Over a bandwidth of 10Hz to 100kHz, there appears to be no oscillation.

[jfedison741]

Is this something related to thermals?
The part is expected to shift quite a bit over line, load and temperature.

Are you concerned with hundreds of microvolts of DC shift?

It doesn't seem to be thermal related. Placing a clear poly bag close by, the shift is much higher, a bit more than 5mV. Yes, a pretty small shift but still trying to understand why it occurs. I have tried other low noise LDO's in the same setup and they don't seem to have this "object proximity" related output voltage shift.

[mawyatt]

Over a bandwidth of 10Hz to 100kHz, there appears to be no oscillation.

(Attachment Link)

If it's oscillating, then likely higher than 100KHz.

Best,

[SiliconWizard]

What's up with the zip lock bag though?

[jfedison741]

Over a bandwidth of 10Hz to 100kHz, there appears to be no oscillation.

(Attachment Link)

If it's oscillating, then likely higher than 100KHz.

Best,

Thanks. I looked out to 20MHz and 300MHz (attached) and it looks like it is a dc effect. In peak detect mode with 10x probe and dc coupled, there is noise about equal to the scope noise floor (probe tip shorted to ground). If there is oscillation, then it would have to be below the scope noise floor. The traces below with steps are when I moved a poly bag near and far from the device every approx. 1.5 sec.

[duak]

You mentioned in your original post that you did not connect the EPAD terminal on the bottom of the device to anything.  The datasheet doesn't come out and say that it must be connected, but on page 6 it highly recommends that it be tied to the board's ground plane.  Since this is a CMOS device and because EPAD is probably connected to the substrate of the die, the device might be more sensitive to electrostatic fields.  IOW, you have an electrometer.

I would try connecting EPAD to the ground plane.  If it is no longer accessible, I would try electrically screening the top surface of the device with a metal plate or screen tied to the ground plane and repeating the test with the eraser or zip lock bag.  If you have a high voltage source of, say 100 to 1000 VDC, I would carefully wave an insulated test probe with that voltage on it near the device and see what happens.

Best o' luck,

[jfedison741]

You mentioned in your original post that you did not connect the EPAD terminal on the bottom of the device to anything.  The datasheet doesn't come out and say that it must be connected, but on page 6 it highly recommends that it be tied to the board's ground plane.  Since this is a CMOS device and because EPAD is probably connected to the substrate of the die, the device might be more sensitive to electrostatic fields.  IOW, you have an electrometer.

I would try connecting EPAD to the ground plane.  If it is no longer accessible, I would try electrically screening the top surface of the device with a metal plate or screen tied to the ground plane and repeating the test with the eraser or zip lock bag.  If you have a high voltage source of, say 100 to 1000 VDC, I would carefully wave an insulated test probe with that voltage on it near the device and see what happens.

Best o' luck,

Thanks for the suggestion. Perhaps the datasheet contains an error but Table 5 of Rev E indicates that the EPAD is electrically tied to GND:
"Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal
performance and is electrically connected to GND inside the package. It is highly recommended
that the EPAD be connected to the ground plane on the board."

So I think the recommendation is from a thermal standpoint. Just to confirm, I will de-solder one of the regulators and measure the resistance from EPAD to a ground pin. If the resistance is low, then I assume that electrically, a connection from ground plane on the board to EPAD would make little to no difference (electrically). Unfortunately, my board does not have a pad on the board to solder the EPAD to.

[Someone]

the device might be more sensitive to electrostatic fields.  IOW, you have an electrometer.

A possibility, but if the epad is connected to GND internally (as the data sheet says it is) then the only high impedance node left is the nc (no connect) pin. It would be funny if that is the source of this, and the nc pin needs a guard trace to meet the OPs requirements desires.

[duak]

I suppose what I'm wondering is how good the connection between GND (or Vss) and the substrate is.  If my memory of CMOS is correct, the substrate is lightly doped P material and forms the lower half of the N channel MOSFETs.  Any variation of the substrate voltage relative to GND will modulate the threshold and conductivity of the N-MOSFETs.  In a digital circuit a change of a few mV is no biggie, but in an analog circuit it's certainly measureable.  I don't have one of these chips here and the drawing in the data sheet isn't too clear but it doesn't look as if the lead frame has the two GND pins solidly connected to the EPAD.  It could mean that the substrate is connected to GND on the chip itself and, if memory serves, could be a fairly high resistance or even a schottky diode.

This isn't my first rodeo - data sheets don't have every bit of info that they could and sometimes what's in them is unintentionally misleading.  The reader understands what the writer said one way but it's not necessarily what the designer and fab actually built.  Didn't Reagan say "trust but verify"?

As Somone points out the NC pin could also be a path to introduce voltage variations into the circuit.  I see on page 6 the admonition: "Do Not Connect to this Pin."  I get the idea that I must not connect to this pin but don't know why I shouldn't.

Cheers,

[SiliconWizard]

Interference from electrostatic fields sounds like a possibility here indeed. That would explain the weird plastic bag thing that probably holds a significant charge when you hold it and move it around.

[jfedison741]

Just an update:

1. I measure resistance > 60 Mega Ohms between the EPAD and either ground pin (3 or 6) (i.e. the datasheet is erroneous about claiming internal connection between EPAD and GND)

2. When I place a grounded screen over the NC pin (pin 4), the dc shift due to moving a poly bag near or far is eliminated (variation in Vout is no longer visible at 10mV/div, dc coupled). With no poly bag nearby, when I move the grounded screen away from pin 4, I get a very clear dc offset in Vout of about 10 mV.

So if using this part, proper guarding of the NC pin is advisable. The picture below shows the grounded screen I used for this test. Note pin 4 of the IC is lifted slightly off the board so it does not make contact to the pcb below. The pcb is a SOIC8 to DIP adapter as shown.

[duak]

It would be interesting to see if the NC pin is connected to something on the chip or if it's just part of the leadframe.  What is the resistance from the NC pin to the other pins, (especially the GND and VIN pins) with a DMM on diode test range?  Might be a clue if it's connected to some internal node, say for test, trimming or an undocumented feature.

Have you tried electrically grounding the EPAD and measuring the output voltage while moving the objects around?

Cheers,

[magic]

Or what's the NC pin open circuit voltage when the chip operates.

[jfedison741]

Problem solved:

Ok, I decided to move the input and output capacitors to be as close as possible to VOUT-GND and VIN-GND and after doing this, I am getting stable Vout with no anomalous dc shifts. See modified setup in the picture attached.

Near as I can tell, my old setup provided lots of loop inductance for both Cin and Cout and this my have been causing instability internal to the regulator. With that setup, when I probed Vout to GND using a 10:1 probe and (short) spring-clip ground connection, I was not able to see any oscillation at least to the 300MHz bandwidth of the probe, down to 10mV/div. Probing was done at the IC pins, of course I could not probe at the chip side of the wire bonds. This makes me think if there was oscillation, it was internal to the IC.

So a note when using this regulator: make sure the connection paths for Cin and Cout are as short as possible and be sure to use a low inductance connection between the GND pins (pins 3 and 6).