Author Topic: Amplifier stage explaination  (Read 2476 times)

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Offline texaneTopic starter

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Amplifier stage explaination
« on: January 10, 2016, 07:52:47 am »
Hi !

I got the following schematics from a magnetic anti levitator project here:
http://www.thingiverse.com/thing:943091

Works fine, but I have trouble understanding the comparison stage. I
understand the operational amplifier is used as a comparator, but what
are C4/R2 used for ? (cf. attachment) . Is this damped integration?

Thanks a lot for your help !
 

Offline dom0

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Re: Amplifier stage explaination
« Reply #1 on: January 10, 2016, 08:57:49 am »
The 5532's common mode input range does not extend to ground, so if R1 is set to "A" the 5532 can do whatever it likes.
The output range is okay, but only with this specific MOSFET, no logic-level MOSFETs allowed.

C4/R2 are frequency compensation, but the value of R2 looks bogus. 6.8 k? is more realistic, possibly less.
,
 

Offline T3sl4co1l

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Re: Amplifier stage explaination
« Reply #2 on: January 10, 2016, 09:31:10 am »
Well, there's about a dozen things wrong with this circuit...

But generally, when you see a C, R+C or other timing network around an op-amp, it's being used as an error amplifier.  Not a comparator.

The distinction is very particular.

At DC, there is no difference: except for an error amplifier of limited DC gain (no integral term), the output of an error amp will be saturated, just as a comparator's will.

At high frequency, the difference is significant.

A comparator is intended to produce its comparison as quickly as possible, on the order of nanoseconds.  It's supposed to look comparator-ey from DC to quite high AC frequencies.

Op-amps (specifically, of the dominant pole compensated type, but that's not important just yet), and error amps in general, are designed to produce a slow, gradual response to an input.  The gain goes from very high near DC, down to unity (1) at some cutoff frequency, give or take some desired characteristic.  They are designed for use in a feedback loop, so that changes in the load can be adjusted for in real time.  The frequency characteristic is necessary to account for delay and lag in the load: obviously, one cannot achieve a stable control (meaning, the change over time eventually goes to zero and it stabilizes) if the load is always being switched suddenly on and off due to every tiny little fluctuation!

Applying some math, one can determine just how slow and gradual the error amp must be, for a known load.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
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Offline texaneTopic starter

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Re: Amplifier stage explaination
« Reply #3 on: January 10, 2016, 10:20:18 am »
Thanks a lot to both of you for the answers ... they explain everything I need to understand this (class of) circuit, esp. the error amplifier stage. I may try to improve it, so any idea / comments is welcome !
 

Offline Kleinstein

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Re: Amplifier stage explaination
« Reply #4 on: January 10, 2016, 10:34:30 am »
In the plan the feedback through R2+C4 is from the inverted output signal to the inverted input - thus this is actually possive feedback. So the OP will oscillate. This may well be intentional to make it a kind of switched mode converter - not just a llinear regulator.  However the size of the MOSFET and the small diode are somewaht strange - a really large MOSFET and a tiny diode.
Depending on the power I would suggest a larger diode like UF4001 or 1N5818. Also the size of C4 is way to large for this type of operation. So the circuit is just strange.

If linear operation is wanted, the frequency compensation should go from the output of the OP, not from the MOSFET, and likely also other values  (smaller resistoance and capacitance).
 


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