Analog current shutdown circuit

[Alaezae]

I'm working on a relay drive circuit, and one of the requirements is to have some kind of analog shutdown functionality for an overcurrent condition. I came up with a circuit in LTspice that seems to work okay, but I'm a little lost on how to handle analysis of the circuit. I would like to define an expression which relates two resistors to the maximum current limit of the circuit. I would also like to determine how temperature will play into the current setpoint. I'm not asking for a fully-fledged solution, but just some directions to search and some ways to attack the problem.

I've attached a simulation of the circuit and will reference the designators from that here.

I was originally working with the circuit without R1. As far as I understood it just by looking at the circuit, a voltage of around 0.7V would push Q3 into saturation and clamp M1's Vgs to 0V. This would shut off current through the sense resistor and set the gate high again. From there, the current would switch on and off through M1. The point of the cap C1 was to adjust the switching time.

After simulating, I found that this was not the case. When in the overcurrent state, Q3 does not switch all the way off, but instead adjusts its voltage based around the amount of current through R3. This pulls M1 into the linear region to regulate the current into the load instead of switching it on and off. The only issue is that the current limit without R1 is based solely on the transistor parameters of Q3, which is undesirable. I would like to be able to control that current setpoint, which is why I added R1. Because M1 is in the linear region, the overcurrent limit which the values of R1 and R6 set are not as easy to calculate with just voltage divider rules. I want to know how to set these two resistors for a certain current limit.

From a digital control perspective, this is exactly what I want because I'm also monitoring the current into the load via R3 (not shown in the simulation, but it's just a current-sense amp). Should an overcurrent event occur, the processor could notice without the current switching back off again. I can still keep M1 within the SOA because of the overcurrent circuit, but the overcurrent event is detectable by my processor. This is why I have chosen not to go with a comparator overcurrent detection which performs the switching action described above.

I've simply adjusted the two resistors via tuning in LTspice, but I'm betting that parasitics will play a role once this is actually built up. I would like to have a deeper understanding of how to adjust this on-the-fly beyond just knowing a simple relationship in LTspice. From my understanding, the Q3-R1-R6-R3 loop is acting like a transimpedance amplifier which watches the current on the resistor R3 and adjusts the gate-source voltage accordingly. I'm a little lost in how to analyze this though and any help would be much appreciated.

FYI, I've just used generic components in the LTspice model and didn't analyze current limits or anything. Just wanted to get the simulation to work.

[Doctorandus_P]

Q3 does not go suddenly into saturation, it just gets opened when Vbe gets around 600mV, and it's base current is limited by R6, and thus the (maximum) collector current is Beta x bigger.

In addition, your FET: https://www.vishay.com/docs/66831/si7469adp.pdf is optimized for switching behavior. A lot of such fets misbehave when you attempt to use them in their linear region, because the threshold voltage is not the same over the whole chip surface.

[Alaezae]

What am I looking for then in FETs meant to be used in the linear region? I was mostly trying to choose it to handle the overcurrent condition within the SOA of the part. In addition, normal operation won't put M1 into the linear region. It would only be pushed there in an overcurrent condition.

I have spec'd a different transistor in my actual circuit, but I changed the part around because the model was not working in LTspice. I'm using a SUM110P08-11L-E3. I suppose that part probably exhibits the same issue.

[Doctorandus_P]

Well, it has a SOA rating, so that's a plus. You've set your current "detection" to: 600mV/0.05 = 12A

With your 28V power source, The SOA is 70mA of DC current, so there is a bit of a gap left.

[MariuszD]

The advantage of a current limiter with a single transistor is its simplicity. This circuit is not precise, and when you add adjustment circuit, the temperature dependence will be amplified.

I did a simulation for two temperatures, 20°C and 40°C, the limiting current changed from 340mA to 736mA.
Without an adjustment circuit, with the same temperature change, the current change would be from 11.9A to 12.6A.

[PCB.Wiz]

What am I looking for then in FETs meant to be used in the linear region? I was mostly trying to choose it to handle the overcurrent condition within the SOA of the part. In addition, normal operation won't put M1 into the linear region. It would only be pushed there in an overcurrent condition.

You also need to watch total power.
You can add current foldback by move of R1 from gate to drain.
Sweep a load in spice and you can adjust the foldback amount.

[PCB.Wiz]

I'm working on a relay drive circuit, and one of the requirements is to have some kind of analog shutdown functionality for an overcurrent condition.

You do not state the relay load, so here is an example for a 25'C peak current limit of appx 4.4A (that's a big relay!)  and a foldback limit at 75'C of 488mA or 13W
The peak power during foldback is ~ 41W, and it will somewhat thermally regulate with a continual short circuit. Power drops as temperature increases thanks to VBE.

I can still keep M1 within the SOA because of the overcurrent circuit, but the overcurrent event is detectable by my processor.

If the MCU can detect an overload, you may be OK with a modest foldback. The foldback may allow you to choose a smaller FET.

In the tests below, one copy tests the power-up load-line ramp, and the other tests the current foldback on a decreasing clamped output voltage.
After the ramp a std off-on cycle checks powered operation.

Addit: Another variant added.
You can increase the foldback action so I = 0 at short, and then add an impulse circuit to the turn ON, to overcome the slight saturated clamp PNP.
In use, the MCU would detect the snap off and cycle the On request.

[Terry Bites]

If your circuit has a 28V supply and a 0.006R coil resistance and without SC protection you get a current of 4666.66A in the relay coil.
Is that right?

For correct operation a relay needs to be on or off, full coil current or zero. (Yeah,yeah, you can back off after pull in). A relay dithering around it operating points might have severe consequences for downstream circuits. Contact burn-out or weld-shut may result. It won't be just your teeth chattering.

Back to the simulation.
With 5A flowing in the steady state circuit (AFAICS) you have 28V*5A =140watts of power being drawn from the 28v bus. Where is that going but into the poor 50W mosfet. Meltdown expected, wheat is growing thin........ With this foldback scheme and its roasting MOSFET you could set fire to something expensive. Can your battery and wiring survive the death of your protection circuit? With a fully melted internally shorted MOSFET and 0.05R of sense resistor in tears that still 56A! R7, why?


Relay coils mostly fail open and rarely short.
A PTC (poly) fuse my be better suited to this application. An NTC thermistor strapped to the coil and a 393 comparator perhaps.
Use an SSR instead?

You'd most likely want the driver to latch off and stay off even after power down. There are special ics for that. eg MAX17523A.

Its usually best to to describe circuits in their operating context. eg What is this monster 0.006 ohm coiled relay and what is it you protection from? What is downstream of it's contacts? What kind of environment is it used in, hobby, automotive, consumer, research, industrial, aerospace etc. Peak the interest of the responders.