Author Topic: analyzing current limiting switch circuit  (Read 1344 times)

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Offline john23Topic starter

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analyzing current limiting switch circuit
« on: February 10, 2026, 07:07:36 pm »
Hello, There is a current limited switch shown below.
could you give basic specs for such circuit?

R2 R1 R5 are important because they deside currents which cause voltage drops which desides the operation mode of Q1 and Q3.
how would you use the simulator to deside the R1 R2 R5 values?
Thanks.
 

Offline Benta

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Re: analyzing current limiting switch circuit
« Reply #1 on: February 10, 2026, 08:34:31 pm »
The only important resistor is R5, which sets the limiting current. When the voltage across it exceeds the VBE of the sense transistor, the PMOS starts turning off.
The rest is on/off control and gate voltage setting.
 

Offline Andy Watson

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Re: analyzing current limiting switch circuit
« Reply #2 on: February 10, 2026, 08:44:50 pm »
how would you use the simulator to deside the R1 R2 R5 values?
I wouldn't!
I would assume that the current limit starts to operate when approx 650mV is developed across R5. If you want more accuracy you will have to take temperature into consideration which will affect the current limit by approximately 4mA per degree (Kelvin.)
 

Offline john23Topic starter

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Re: analyzing current limiting switch circuit
« Reply #3 on: February 11, 2026, 03:00:06 am »
sorry for the question , what would your strategy to deside the values of R1 R2 given the simulation.
Thanks.
 

Offline john23Topic starter

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Re: analyzing current limiting switch circuit
« Reply #4 on: February 12, 2026, 06:13:45 pm »
Hello , We have Q3 which is controlling the p-channel mosfet.

When Q3 is open then Vgate of the mofet is 12V and mosfet source is 12-0.7V(Vbe condition of Q3)
So Vsg of the mosfet will be -0.7V .
Three questions :
1. PMOS cannot open with Vsg -0.7 where is my logic wrong?
2.How can we know the Q3 will be open?
3.Do we need to use p-channel enhasment mode for this case?
 

Offline Benta

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Re: analyzing current limiting switch circuit
« Reply #5 on: February 12, 2026, 07:35:49 pm »
Hello , We have Q3 which is controlling the p-channel mosfet.

When Q3 is open then Vgate of the mofet is 12V and mosfet source is 12-0.7V(Vbe condition of Q3)
So Vsg of the mosfet will be -0.7V .
Three questions :
1. PMOS cannot open with Vsg -0.7 where is my logic wrong?
2.How can we know the Q3 will be open?
3.Do we need to use p-channel enhasment mode for this case?
1: the PMOS will turn on when input is 3.3 V, meaning Vgs is around -8 V.
2: because ther's not enough current through the sense resistor to turn it on.
3: no.
 

Offline john23Topic starter

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Re: analyzing current limiting switch circuit
« Reply #6 on: February 14, 2026, 09:15:58 am »
Hello ,Q1 NPN ,Q3 is PNP Q2 is enchament mode P-channel mosfet.
given  Q1 is 2N3904 Q3 is 2N3906 Q2 is IRF5305,I assume that we want Q1in saturation when they are ON because VCE is very small and its the closest to short circuit.

1.Q1 is in saturation when Vce=0.2
12−I⋅50K−0.2−I⋅15K=0
I=0.182mA
given the datasheet how can I know that when Ic=0.182mA Vce will be 0.2V?

2.
V_e_q3=12V
V_c_q3 =12V-0.128mA*50Kohm=5.6V
Vec_q3=6.4V which is by far not a saturation state give such large Vec.
but basickally How can I know that Q3 is even open?
How can I know given the datasheet the base voltage of Q3 ?
2N3904
https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/4846/DS_497_2N3904.pdf
2N3906 PNP
https://www.onsemi.com/download/data-sheet/pdf/2n3906-d.pdf
 

Offline john23Topic starter

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Re: analyzing current limiting switch circuit
« Reply #7 on: February 15, 2026, 12:39:52 pm »
Hello , I understand that the ratio between them desides the state of NPN Vce
So We know the VCE of Q3 shown below.
before going into the mosfet I need to know what is the Base voltage of Q3?
Is there some mathematical intuition Which could help me find Vbase of Q3 shown below?

 

Offline mawyatt

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Re: analyzing current limiting switch circuit
« Reply #8 on: February 15, 2026, 03:11:52 pm »
If anyone decides to built this, add a resistor (~1k) in series with Q3 base. In actual use with a short applied to the output, the high surge current "spike" thru the PMOS will partially pass thru the base-emitter junction of Q3 before the PMOS time-wise begins to limit the current. This current "spike" likely will damage Q3 without the series base resistor.

Best
Curiosity killed the cat, also depleted my wallet!
~Wyatt Labs by Mike~
 

Offline Benta

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Re: analyzing current limiting switch circuit
« Reply #9 on: February 15, 2026, 09:40:13 pm »
You're misunderstanding the circuit a bit.
Q1/R1 is basically a constant current sink, pulling down the gate voltage of the PMOS to around 3.5 V.
R2 is irrelevant as long as it's larger than R1. It's there for helping the PMOS turn off when the control input goes to 0 V. The way the circuit is drawn doesn't make this clear. It does not have influence on general operation.
Q3/R5 has already been explaind, but mawyatt's input is good, a base series resistor of around 200 ohms is sound design practice.

« Last Edit: February 15, 2026, 09:47:07 pm by Benta »
 

Offline john23Topic starter

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Re: analyzing current limiting switch circuit
« Reply #10 on: February 16, 2026, 03:07:30 am »
Hello,When Vin=0 Q1 is not conducting so the potential on both R2 ends is 12V So Q3 .
what about the base of Q3 , purely on logical level is there some way i could asses its situation?
So I'll know if Q3 is conducting or not?
 

Offline Benta

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Re: analyzing current limiting switch circuit
« Reply #11 on: February 16, 2026, 11:26:10 am »
Q3 will only start conducting when the voltage over the sense resistor is larger than the VBE(ON). If not, BE is practically shorted by the sense resistor, so no conduction.
 


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