analyzing pulse generating circuit

[john23]

Hello,in the book the art of electrnics there is the following circuit.
the npn's are used as switches.
how exactly the C1 capacitor works in controlling the rise and fall moment of the pulse.
what is the math on generating this pulse?
the verbal explanation is not clear.
how the capacitor controls the state of the npn?
Thanks.

[PCB.Wiz]

This is a great example for learn by doing.
The circuit is simple and the waveforms are shown.
Put it into any Spice and you can vary C1 to see how exactly the C1 capacitor works in controlling the rise and fall moment of the pulse.
You can also vary R1 thru R4 and even change transistor types to see what effect they have.
If you need a very fast fall time, some Schmitt action will need to be added.

[SiliconWizard]

So, basically:

1. In the "idle" state (Vin = 0, steady state): Q1 is OFF, so C1 is discharged through R2 and R3. Its potential difference is thus near zero, so you can consider that the circuit to Q2's base is VCC -> R2//R3. So, Q2 conducts (in saturation) and thus holds Vout at near zero.

2. When Vin transitions to +5V, Q1 starts conducting, so the voltage at its collector drops. When Q1 saturates, it connects its left end to GND. As C1 is initially discharged, what follows is that Q2's base is now at a near-zero voltage, and stops conducting. So Vout rises to Vcc via R4.

3. As long as Vin remains high, C1 gets charged through R3 and Q1, and so Q2's base voltage rises exponentially, until it reaches Q2's threshold. Then Q2 starts conducting, and Vout falls back. It will remain in that state until Vin itself falls back, and then the circuit gets back to case 1.

What determines the "pulse width" here is C1, R3 and Q2's threshold voltage.

C1/R3 have some impact on the fall time as Q2 transitions to saturation, but most of it comes from R4 and Q2's parasitic capacitances.

As to the rise time, it mostly comes from R1 and Q1's parasitic capacitance. There's also the question of the delay between the rising edge of Vin and the rising edge of Vout, which isn't shown on the book's waveforms.

Of course, this is still a simplified analysis. We could make it almost as complex as possible if taking all parasitics into account, the rise time of Vin, the parasitics of the voltage source for Vcc, the transition between linear and saturation regions for the transistors...

[CountChocula]

So, basically:

Interesting—I was writing this response while you posted yours, and there are some differences that intrigue me… not to hijack the thread, but can you help me understand where I went wrong?

Thanks!


-CC

• First of all, we can more or less ignore R1 and R4, as they are there as current limiters on the base of Q1 and the collector of Q4 respectively. Without them, we would short to VCC to ground, but otherwise they have no impact on the circuit for the purposes of understanding how it works*.
• Next, let's pick a starting state. When in is low, Q1 is off, and therefore the left-hand plate of C1 is held to 5V through R2. Meanwhile, the base of Q2 is pulled high by R3. This means that the transistor is on, and therefore out is low. It also means that the right-hand terminal of C1 is held at around 0.6V (a diode drop). At steady state, you therefore have low in, low out, and C1 with a stored charge of ~4.4V. Importantly, if you look at voltage across the capacitor using its left-hand plate as the ground reference, the right-hand plate has a voltage of -4.4V.
• If you now pull in high by connecting it to VCC, Q1 quickly turns on, bringing the left-hand terminal of C1 down to ground. At this very instant, therefore, the left-hand plate of C1 is at 0V using the circuit's ground as a reference, and the capacitor starts to move its charge out of the right-hand terminal. This cannot happen instantaneously, however, because that would require an infinite amount of current. Therefore, you now have 0V on the left-hand terminal, and (counterintuitively) ~-4.4V on the right hand terminal. This turns off Q2, which brings out high.
• Over time, C1 equalizes its charge through R2, and eventually the right-hand terminal goes back above 0.6V, turning Q2 on again and bringing out low once more. This creates our pulse.
• When you bring in back low, Q1 turns off again, and the left-hand terminal of C1 is pulled back up to 5V, at which point the circuit is ready for another cycle**. R2, therefore, controls the retrigger rate of the circuit.

The capacitor's behaviour is counterintuitive (or, at least, it was to me when I first started out) because it seems to manufacture negative voltage out of nothing, but it makes sense when you consider that voltage is always expressed relative to some ground reference, and that current cannot be truly instantaneous. When one terminal is forced to move, the other must move as well to preserve the existing electric field.

We can now consider the role of R2 and R3: The RC constant formed by R3 and C1 determines how long the pulse lasts, whereas the RC constant formed by R2 and C1 determines how long it takes for the circuit to recover once you turn in low after bringing it high and causing a pulse to be output.


* This is not entirely true. R1 must let enough current through to actually saturate Q1 given the collector current set by R2, and its value determines how quickly the circuit responds to a change in input, while R4 determines the rise time of the pulse together with any output capacitance.

** In reality, the circuit will be “reset” as soon as the left-hand terminal of C1 is higher than the right-hand terminal, but the pulse length will be affected, since the voltage differential across the capacitor is not at its maximum.

[Andy Watson]

1. ...   so C1 is discharged charged (+ve to R2)  through R2 and R3 the B-E junction of Q2, which limits the base potential to appox +0.6V. Its potential difference is thus near zero approx 4.4V (+ve to R2), ...

2. ...  As C1 is initially discharged charged to 4.4V, what follows is that Q2's base is now at a near-zero -4.4V voltage, ...

Some minor corrections - it will make a big difference to the time constant!

[SiliconWizard]

1. ...   so C1 is discharged charged (+ve to R2)  through R2 and R3 the B-E junction of Q2, which limits the base potential to appox +0.6V. Its potential difference is thus near zero approx 4.4V (+ve to R2), ...

2. ...  As C1 is initially discharged charged to 4.4V, what follows is that Q2's base is now at a near-zero -4.4V voltage, ...

Some minor corrections - it will make a big difference to the time constant!

Ah, right. Pesky bipolars, I'm too used to using MOSFETs now.

So yes, the capacitor will be charged to about 4.4 V when Vin is zero and then discharges when Vin is high and reverses to about -600 mV. (Or the opposite, depending on which direction you define your capacitor's potential difference).
So it's actually never fully discharged, except for a very short instant.

[shapirus]

Also a good simple qualitative way of understanding how capacitors work in cases like this:

- when the capacitor is not charged, it appears as a short to the (DC) voltage that's applied to it;
- when it is fully charged, it appears as an open circuit;
- between these two states its "apparent resistance" to DC voltage increases from zero to infinity.

[john23]

1.what is " Q2's base is VCC -> R2//R3." the base cannot be VCC because Vbe in forward active is 0.7V?


2.in t=0 the C1 is not charged because potential difference is zero. why did tou say its discharges when pulse rises?

[john23]

"Over time, C1 equalizes its charge through R2, and eventually the right-hand terminal goes back above 0.6V, turning Q2 on again and bringing out low once more. This creates our pulse."

so capacitor has 0 volts of left side and -4.4V on right side.

the pulse is still high Q1 is open so C1 left side is left 0V potential when pulse high?
C1 right side potential gets charging from R3?

[john23]

"R2, therefore, controls the retrigger rate of the circuit."

why it controls the retrigger rate?

[SiliconWizard]

So: my first post was a correct analysis... for N-channel MOSFETs rather than NPN transistors. So that gives you the behavior for MOSFETs.
My answer was then corrected in my second post for NPN transistors, as shown in the schematic you posted. Sorry for the confusion.

1. Q2 base at VCC through R2 parallel to R3 in the "idle state" was correct again in the case of MOSFETs. I fixed it in my second post.
2. Same, it was for MOSFETs.

Read my second post for the corrections.

We can add a bit though: there is a transient state at power-on if we assume C1 is initially discharged:

- At power-on (but Vin = 0 V), C1 will charge through R2 as Q2's BE junction essentially acts as a forward-biased diode. So C1 will get charged to (VCC - Vbe) ~ 4.4 V.
- When Vin rises above Q1's threshold voltage, C1 will discharge through R3. Since the right end is still at ~ 0.6 V and the left end is pulled down to near 0 V when Q1 saturates, C1 discharges and its potential diffference tends  to ~ - 0.6 V.

So, the *steady* states are:
* Vin low   => V(C1) ~ +4.4 V
* Vin high => V(C1) ~ -0.6 V

Note again the transient phase (both at power-on and when Vin falls back to 0 V) where C1 charges back to (VCC - Vbe), so that if a second pulse is triggered within a certain delay (before C1 is charged back to the "nominal" VCC - Vbe) after Vin has dropped, the second pulse width will be shorter.