Big serial SRAM

[tszaboo]

Hi,
I'm working on a project where I need 1Mbit+ serial SRAM. The biggest I was able to find is the microchip 1Mbit ones, on SPI. But more memory is needed, and there is n way to put parallel memory on the board, because the microcontroller needs to have parallel memory interface for that, thus I need something bigger than a Cortex M0+. So I wonder is there any way to connect big SRAM to a small micro? The budget is thigh, so FPGA or CPLD is out of the question, also those IDT ASICs.
It is obvious that I can put more than 1 SPI SRAM on the board.
Did anyone solve this problem in a different, clever way? Is there someone making a parallel SRAM with a "hidden" serial interface? Mind to share?

[TopLoser]

Micro SD cards are serial interface and only need a couple of control lines. You can get them for less than £1 each for a few GB of storage.

[nctnico]

You can always bit-bang a parallel bus. To safe pins you could use 74xx595 shift registers to make the address lines. On a Cortex Mx you actually need to worry about the access time even when bitbanging a parallel interface.

[tszaboo]

SD card is out of the question, it is flash, unreliable. Few of them are rated to industrial temperatures, where this thing goes.

You can always bit-bang a parallel bus. To safe pins you could use 74xx595 shift registers to make the address lines. On a Cortex Mx you actually need to worry about the access time even when bitbanging a parallel interface.

You are suggesting to make an SPI like interface from 74 series glue logic. Interesting.
Speed is less of a concern, the size is a bigger one.

[Kjelt]

Perhaps you can specify the requirements somewhat more precise.
From what you have told thusfar I deduce:

- interface: serial SPI
- size >1Mbit
- speed not an issue
- volatile storage allowed, power down data lost
- operating temperature 125^oC

It misses:
- how many write cycles endurance?
- how long minimum storage lifetime in years with 125^oC
- how large exactly >1Mbit how much bigger? 2Mbit, 64 Mbit

What you told us thusfar the requirements are not for a single technology.
Normally the difference between choosing SRAM vs FRAM vs EEPROM vs FLASH are something like:

Technology:     Memsize:       avg. write cycle endurance:     Relative pricefactor:      Byte/Page write time
               
FRAM             upto 256 kbit     1000000000000                    60                                          0
SRAM              upto 1Mbit       1000000000000                 30(have to check)                                        0
EEPROM         upto 512 kbit     4000000                                 13                                       5 ms
FLASH            upto 512 Mbit    100000                                  1                                           0.8 ms

There are  a lot of SPI Flash chips that endure 125^oC, and with some errorcorrection/checksums the biggest problem is the write cycle endurance.
You will need a form of wearleveling in your software and even then it might quit on you. On the other hand it is dirt cheap (in comparison) so if you take a 10 times bigger chip then really needed you can afford to loose some pages along the way, just keep track of them in your filesystem.

So what do you need exactly is it really for instance 8Mbit SRAM or can it be done with 1Mbit SRAM as buffer and 32Mbit Flash as storage.

[fcb]

Not entirely what you are after.  I did a project awhile back where I needed a heap of FLASH and it had go fast - I used 8 serial devices effectively in parallel (so each part was playing out a single bit, effectively multiplying the byte throughput by eight).

[hli]

Cypress has 2MBit F-RAMs available: http://www.cypress.com/?id=4984. Everspin has 4MBit serial SRAMs: http://www.everspin.com/products.php?hjk=SERIAL&a1f3=0

[tszaboo]

Yes, life endurance is a problem. It doesnt need to work at 125C, 85C devices are fine, but SD card is not, and I would not put there flash memory at all. Fram and Mram is out of the budget, it needs to be close to the 4 USD (@1000) price of the two 23LC1024 from microchip to consider. Sram is the correct technology to use, with battery backup
Personally, I would go for the SRAM+Flash combo, but the programmers are not happy with it. They tried

So to answer your question:
SPI or maybe I2C
2-4-8 mbit
Some 100Kbit/sec speed
85 degrees
battery backup (which is fine) or non volatile (which is either flash or not cheap)
endurance is necessary, it needs to be at least as endurable as an EEPROM
Price about 4-6 USD in 1000 quantity

[David Hess]

Assuming that you can get the required speed from a single serial SRAM, then I think your best option is to use multiple serial SRAMs.  If I wanted more speed, I would use 4 or 8 in parallel and implement a parallel SPI or I2C interface but interfacing with the microcontroller could be a problem and it would take more I/O pins.

An external 3-to-8 decoder could be used to minimize the number of pins required for SPI chip select or chip select could be generated by an I/O expander.  I2C would have an advantage here as far as the number of pins required.

If I wanted a lot more capacity, then I would implement a full parallel interface on an I/O expander and use a parallel SRAM.

[ovnr]

Just buy several chips? 1Mbit SPI chips are around $2/pop (1k).

Just parallel up the MISO/MOSI/CLK pins, and run separate CS lines. If you absolutely must have a continuous memory space, emulate dual/quad SPI by running data lines separately too, but you'd need to emulate it in software.

Or you could always stick on a CPLD + some parallel SRAM. 8 Mbit of parallel SRAM can be yours for $3.70 (1k) + $1-2 for a CPLD with glue logic.

[tszaboo]

Assuming that you can get the required speed from a single serial SRAM, then I think your best option is to use multiple serial SRAMs.  If I wanted more speed, I would use 4 or 8 in parallel and implement a parallel SPI or I2C interface but interfacing with the microcontroller could be a problem and it would take more I/O pins.

That is clearly possible, that is the original solution I mentioned in the first post. I was wondering if there is a parallel memory with serial interface, because I remember I saw it somewhere. And indeed, I found it, it is the Micron PCM memory.

"A serial peripheral interface has been added as a secondary interface on P8P parallel
PCM to enable low cost, low pin count on-board programming. This interface gives
access to the P8P parallel PCM memory by using only seven signals, instead of a conventional
parallel interface that may take 45 signals or more."
Now, PCM is unfortunately dead, and it doesnt look like others used this interface.

[mikeselectricstuff]

Cheapest for production volumes would be a parallel SRAM as big as you need plus a small CPLD to handle SPI interfacing.
Though you may find that multiple SPI RAMs could be a simpler solution.
 

[tszaboo]

Cheapest for production volumes would be a parallel SRAM as big as you need plus a small CPLD to handle SPI interfacing.
Though you may find that multiple SPI RAMs could be a simpler solution.

4 megabit parallel sram is about 2,5 USD, and a 128 macrocell CPLD is about the same. So I guess this might be indeed viable.

[David Hess]

That is clearly possible, that is the original solution I mentioned in the first post. I was wondering if there is a parallel memory with serial interface, because I remember I saw it somewhere. And indeed, I found it, it is the Micron PCM memory.

"A serial peripheral interface has been added as a secondary interface on P8P parallel
PCM to enable low cost, low pin count on-board programming. This interface gives
access to the P8P parallel PCM memory by using only seven signals, instead of a conventional
parallel interface that may take 45 signals or more."
Now, PCM is unfortunately dead, and it doesnt look like others used this interface.

I never considered this a feasible solution because a specialized memory would be more expensive than something available from multiple sources.

There is a parallel version of SPI which I discounted for the same reason.

All of the other options I found were more expensive than using multiple 1 Mb serial access SRAMs.

[Scrts]

Your only option is to use several of SPI SRAMs.
If you would consider parallel SRAM plus CPLD, include all the decoupling needed for the CPLD, plus programming header, some pullups/pulldowns, PCB area, effort to do the CPLD design, better power supply, that would provide enough current... Probably it's not the end of the list. I imagine you will need better than commercial grade CPLD, so check the price of the industrial one.

I didn't quite get the point. You have a microcontroller, that has the parallel memory interface, but this is already used for another purpose? Usually, those interfaces can be shared between multiple devices.

[mikeselectricstuff]

Cheapest for production volumes would be a parallel SRAM as big as you need plus a small CPLD to handle SPI interfacing.
Though you may find that multiple SPI RAMs could be a simpler solution.

4 megabit parallel sram is about 2,5 USD, and a 128 macrocell CPLD is about the same. So I guess this might be indeed viable.

you wouldn't need anything like 128 macrocells. should be doable easily in 64, which is a lot cheaper.. All you need is a shift register for address and another for data
if you don't want to get into CPLDs then you could also easily  it with an MCU, but CPLD will probably be cheaper due to the number of pins. Another, possibly cheaper  option if speed isn't an issue is a bunch of HC595s, a parallel in register (don't recall HC number offhand) and and a couple of extra control lines. This would also be very low power, close to zero when idle.   

[mikeselectricstuff]

Your only option is to use several of SPI SRAMs.
If you would consider parallel SRAM plus CPLD, include all the decoupling needed for the CPLD,

Negligible

plus programming header

PCB pads, or could be programmed by the MCU

, some pullups/pulldowns,

What for?

PCB area, effort to do the CPLD design

Applicable to any solution. If you know HDL then the CPLD design would be simple - a dozen lines maybe.

better power supply, that would provide enough current...

Unlikely to need much - maybe 10-20mA active.

[tszaboo]

I didn't quite get the point. You have a microcontroller, that has the parallel memory interface, but this is already used for another purpose? Usually, those interfaces can be shared between multiple devices.

No, I have a microcontroller (in my proposal) without external memory interface. It is a small 48 pin, M0+. Then they asked for (a lot) more memory. The usual air balloon of the requirements. So we just snapped two SPI SRAM's price to the budget, because we did not had the time to investigate all the options. Now I have the time.

you wouldn't need anything like 128 macrocells. should be doable easily in 64, which is a lot cheaper.. All you need is a shift register for address and another for data

And the OE or the WE signal timing is bit banged? I'm kinda tempted to use a CPLD, I havent had the chance to try them in the past.

But in fact, I came to a conclusion. It is worth to upgrade your microcontroller to a higher pin count one, if you need to have this much external memory. An 1 Mbit SPI RAM costs almost the same as a 2 Mbit parallel SRAM, and it just becomes worse than this above 2 Mbit. Switching from the M0+ to an M3 with 100 pins and memory interface is almost the same cost as one chip of the SRAM! I can design the board with peace in my mind, that more memory will fit in the same footprint. Not to mention the additional benefits of the bigger MCU. This was a bit counter-intuitive.
If your memory costs more than the microcontroller, you are obviously doing something wrong, right? Thanks everyone for the help!

[mikeselectricstuff]

I didn't quite get the point. You have a microcontroller, that has the parallel memory interface, but this is already used for another purpose? Usually, those interfaces can be shared between multiple devices.

No, I have a microcontroller (in my proposal) without external memory interface. It is a small 48 pin, M0+. Then they asked for (a lot) more memory. The usual air balloon of the requirements. So we just snapped two SPI SRAM's price to the budget, because we did not had the time to investigate all the options. Now I have the time.

you wouldn't need anything like 128 macrocells. should be doable easily in 64, which is a lot cheaper.. All you need is a shift register for address and another for data

And the OE or the WE signal timing is bit banged? I'm kinda tempted to use a CPLD, I havent had the chance to try them in the past.

Or you could use HC595 pins for CS,WE etc.

[nctnico]

How about looking for a controller with enough internal SRAM?

[Scrts]

Your only option is to use several of SPI SRAMs.
If you would consider parallel SRAM plus CPLD, include all the decoupling needed for the CPLD,

Negligible

plus programming header

PCB pads, or could be programmed by the MCU

, some pullups/pulldowns,

What for?

PCB area, effort to do the CPLD design

Applicable to any solution. If you know HDL then the CPLD design would be simple - a dozen lines maybe.

better power supply, that would provide enough current...

Unlikely to need much - maybe 10-20mA active.

Regarding pullups/downs -> You probably still need some configurations pins to be set up.
PCB pads for programming means no firmware upgradability for user.

Regarding the HDL coding: if you want something, then yes, it's probably a dozen lines. If you want something really reliable, then it's not so easy.

[David Hess]

But in fact, I came to a conclusion. It is worth to upgrade your microcontroller to a higher pin count one, if you need to have this much external memory. An 1 Mbit SPI RAM costs almost the same as a 2 Mbit parallel SRAM, and it just becomes worse than this above 2 Mbit. Switching from the M0+ to an M3 with 100 pins and memory interface is almost the same cost as one chip of the SRAM! I can design the board with peace in my mind, that more memory will fit in the same footprint. Not to mention the additional benefits of the bigger MCU. This was a bit counter-intuitive.

This also allows fast direct access although in some applications that is not an advantage.

How about looking for a controller with enough internal SRAM?

I hunt for these regularly and always come away disappointed.  Internal program memory sizes increase but they never have enough internal SRAM.  The holy grail for me is a microcontroller in a small but easy to use package with lots and lots of SRAM and enough program memory.

[mikeselectricstuff]

How about looking for a controller with enough internal SRAM?

Because there aren't any.
You just don't get huge RAM on micros. The biggest I know of offhand is 512K on a PIC32MZ

[mikeselectricstuff]

Regarding pullups/downs -> You probably still need some configurations pins to be set up.
PCB pads for programming means no firmware upgradability for user.

It's unlikely you'd need to update something this simple

Regarding the HDL coding: if you want something, then yes, it's probably a dozen lines. If you want something really reliable, then it's not so easy.

Yes it is - it's just a bunch of shift registers, and clock rates will be way below device capabilities so no need to worry about timings

[nctnico]

How about looking for a controller with enough internal SRAM?

Because there aren't any.
You just don't get huge RAM on micros. The biggest I know of offhand is 512K on a PIC32MZ

1Mbit=128KByte so there is enough choice. If a lot of memory is required some of the higher end parts have the ability to use an SDRAM. The multiplexed address bus reduces the number of pins.