BuckConverter not working properly under load

[Phexxtor]

Hi there,
i am new to this forum and it seems like i need some help 

I want to build a buck converter. This is my second try with the IC. Every component is calculated through the TexasInstruments WeBench online tool.
Under slight load the converter is working but when i put more stress on it the voltage drops completely.

I have no idea whats wrong with that circuit.

Attached u can find some pictures

[PGPG]

I have no idea whats wrong with that circuit.

To find the reason compare your 'improved' layout with datasheet example.
Hint: connection between input/output capacitors and Ic GND.

[Phexxtor]

i spotted on little mistake for the avin capacitor but for the output capacitor i cant find any technical differences. 

[d-el]

Under slight load the converter is working but when i put more stress on it the voltage drops completely.

How do you connect the oscilloscope probe? With a long ground alligator?
You need to use a spring on the probe and connect it directly to C3.

[Phexxtor]

How do you connect the oscilloscope probe? With a long ground alligator?
You need to use a spring on the probe and connect it directly to C3.

yes, i used the alligator for ground. Never used these springs before.. i measured again with the spring and the voltage seems very "stable" without these peaks/spikes like in the other pictures before.

With a load of 1amp the voltage drops to 0.7V

[PGPG]

but for the output capacitor i cant find any technical differences.

I'm all the time not sure if file I'm trying to attach will be attached or not as I all the time see 'No file was selected' info.
There is no idea to write about picture that will be not attached.

[ Attachment Invalid Or Does Not Exist ]

Stupid software. File exists and I was selecting it may be 15 times then Cancelling 'to many of them' and left only one, but...

[mtwieg]

I don't see any issue with the layout, but it's hard to tell since most of it's hidden by the soldermask and 3D part models. Need to see vias and other copper layers to be sure.

You didn't mention what Vin is in your setup.

[tszaboo]

I don't see any issue with the layout, but it's hard to tell since most of it's hidden by the soldermask and 3D part models. Need to see vias and other copper layers to be sure.

You didn't mention what Vin is in your setup.

I think there is a lot of vias missing from the layout. Like every capacitor should have 2-3 and the IC should have a half a dozen vias underneath.

How do you connect the oscilloscope probe? With a long ground alligator?
You need to use a spring on the probe and connect it directly to C3.

yes, i used the alligator for ground. Never used these springs before.. i measured again with the spring and the voltage seems very "stable" without these peaks/spikes like in the other pictures before.

With a load of 1amp the voltage drops to 0.7V

Probing power supplies is tricky. Your inductor (ie) will create a lot of EMI that gets into your probe, and appears on the scope.
But that doesn't explain the issue with the loading. Sometimes it's something stupid, like your bench PSU goes into CC mode or you blow a PTC or some other issues. Check that first. What do you use for loading?

[d-el]

i used the alligator for ground. Never used these springs before.. i measured again with the spring and the voltage seems very "stable" without these peaks/spikes like in the other pictures before.

This is only suitable for measuring DC voltage. To analyze DC-DC use a spring.

[Phexxtor]

As load i use three power resistors in parallel. Connected to the psu they draw exact 1amp at 3.3volts.

Vin should be powered by a battery but for testing i use my labbench supply. That is set up correctly and capable of handle that.. i already checked that

[tszaboo]

As load i use three power resistors in parallel. Connected to the psu they draw exact 1amp at 3.3volts.

Vin should be powered by a battery but for testing i use my labbench supply. That is set up correctly and capable of handle that.. i already checked that

Your ground current for those capacitors have to go all the way through your board, and out of this picrure.
Add more vias to ground, and to power. If you think it's enough, then double it.
The distance between the inductor and the output capacitor should be less than 1mm.
Also add more capacitors on the input and output, 2 or maybe 3. The datasheet values are typically minimum values with unspecified noise figures. Worst case you don't need them and they will be empty.
Minimize your current loop. Your loop is IC-> inductor-> output cap ground. The ground current in a buck converter is higher than the power supply current, so add more vias. If you cannot draw this loop in a few millimeters, strart again the component placement.

[MSP_TechLab]

Maybe it is too simple suggestion, but in order to investigate such issue, you shall start from simple things:
- Is your power supply is powerful enough to support your circuit? Even bad power wires can cause DC-DC to fail.
- Are you diodes are properly selected and provides enough current? ( connection diodes in parallel is bit strange solution as for me).
As you have oscilloscope all that can be easily tested.
 

[Phexxtor]

- Is your power supply is powerful enough to support your circuit? Even bad power wires can cause DC-DC to fail.
- Are you diodes are properly selected and provides enough current? ( connection diodes in parallel is bit strange solution as for me).

power supply can handle that.
the diodes in parallel are there because the circuit can be powered by 3 different power signals which should not interfere with another.
and i already tested it without the diodes, so they are not causing this problem.

Your ground current for those capacitors have to go all the way through your board, and out of this picrure.
Add more vias to ground, and to power. If you think it's enough, then double it.
The distance between the inductor and the output capacitor should be less than 1mm.

in this case the groundplane is on top layer and the vias to bottom are just for heat distribution.
the output capacitor is indeed maybe a bit far away..

seems like there are no major mistakes made so i will try to make a new one which is a "copy" of the reference layout. i have no better idea

[HwAoRrDk]

You can get rid of the R9 100k resistor if you're not using the PG output (I don't see anything else connected to it). Just leave that pin unconnected.

The resistor is only necessary because the PG pin is an open-drain output, and so needs a pull-up to function. But when PG is unused, the resistor serves no purpose.

[mtwieg]

Ok I was assuming you had more vias than were visible in the first screenshot, apparently not....

tszaboo is correct, the return path for the input caps is way too long. Should put a few GND vias around C1 and C6.

The routing of +3V3 from L1/C3 is also not good. You don't actually have move C3 or L1 to fix this though. Instead, change the layout such that +3V3 branches directly from C3 instead of from L1. Also add GND vias around C3.

[MariuszD]

the output capacitor is indeed maybe a bit far away..
seems like there are no major mistakes made so i will try to make a new one which is a "copy" of the reference layout. i have no better idea

Converters operating at 1MHz and above are very sensitive to suboptimal layout. A trace a few millimeters long will lower the resonant frequency of the MLCC capacitor below 1MHz.
In the past, I had the same problems with a similar converter, now I know how important it is to minimize the area of current loops.

[Phexxtor]

So, i've done some testing regarding current loops. This is an topic which i was not aware of.

I checked the loop from C3 back to the controller and saw that it is waaay to long. (blue lines in attached pic)
After that i soldered a crucial bridge (red line) to shorten that path and the result was way better. Not working complete properly but the voltage drops "only" to 2.5 instead of 0.7

So it seems that was/is the problem with my circuit.
Thank you all for your input, next time i will take more care on this topic!

[PGPG]

Read once more my first post. If you don't understand read it once more and once more till you understand.

Find the way from Ic GND to input and output capacitors GND pads at datasheet example layout and find that way at your PCB. It is even worse than I expected at the beginning. I supposed that going from IC right under L you go around one L pad and connect to capacitors, but you break there GND connection.

This connection is most critical in this DCDC.

Edit...
I see that when I was writing you showed that you at least understood.

[Phexxtor]

Read once more my first post. If you don't understand read it once more and once more till you understand.

Find the way from Ic GND to input and output capacitors GND pads at datasheet example layout and find that way at your PCB. It is even worse than I expected at the beginning. I supposed that going from IC right under L you go around one L pad and connect to capacitors, but you break there GND connection.

This connection is most critical in this DCDC.

You are right. I have done it in the worst way possible by accident.
Now it makes sense to me why there are five vias between the two input/output capacitors. To be honest i never assumed that this topic has such an influence and thought they were used for better heat dissipation. But glad i could learn something new to improve future designs.

[PGPG]

Draw two circuits:
1. From supply capacitor GND throuh capacitor to its + pin and then through Ic and L to output capacitor + pin and through it to its GND pin and back to input capacitor GND pin.
2. From output capacitor GND pin, through Ic and L to output capacitor + pin and back to its GND pin.

These are two ways current is flowing in your DCDC. They should be as short as possible.
My way (since always) of designing DCDC is by imagining that these two circuits flashes alternatively and designer task is to design circuit the way to make this flashing being not visible from as short distance from PCB as possible.

Recently I have read the different explanation that directs you to the same result but using more electronic explanation than my flashing:
None of these two circuits (as a whole circuit) is the most critical circuit here. Surprise ?! It is because in each of them there is L which protects these circuits against fast current changes.
The most critical circuit is the difference between these both circuits. Even you don't think current ever flows in this circuit it is the circuit with fastest possible current changes so most critical circuit here. It is because there is no L in this circuit. So this is the circuit you should take care first.

[PGPG]

To be honest i never assumed that this topic has such an influence and thought they were used for better heat dissipation.

In past, when DCDC were working with 20kHz frequency their layout was not so critical. For high current DCDC (in my case that means 300mA) I have never decided to use higher than 400kHz switching frequency.

Once more.
Look at example in datasheet. Vias are not important there. The critical GND connection is there made directly at top layer, but in your design you 'improved' layout but cutting this connection to route the track with no pulse current in it.

[squadchannel]

dedicate the bottom layer to GND and connect everything with vias. It may not be perfect, but this is the easiest way to make it work.

[ArdWar]

Looking at the layout, the design priority is indeed all over the place.

• The Pin12 - C6 (and C1) - Pin15 loop i the most critical. Put C1 directly bridging that gap as close as feasible. Worry about everything else later.
• The inductor is unnecessarily too far away from Pin2. Your R9 doesn't appear to do anything so might as well get rid of it so it won't interfere.
• Pickup point for the feedback network should be near the output capacitor pad. I'm unfamiliar with VOS pin, but considering how it's in the control loop I guess it also should be picked off the same location as the feedback network.
• AGND pin is already conveniently near FB pin. It's better to connect the ground leg of the FB divider directly there instead of into random faraway (probably noisy) ground.

[Phexxtor]

Yeah, R9 is unnecsessary in this case. According to datasheet is should be left floating or connected to ground when unused.

For testing i added a second Bridge to GND on the button right corner from IC over the track from L1 and now the circuit can handle the 1amp without any significant voltage drop. (from 3.3 to 3.28)

I thought i was pretty close to the reference layout but was not aware of some of the most critical parts of a DCDC

• AGND pin is already conveniently near FB pin. It's better to connect the ground leg of the FB divider directly there instead of into random faraway (probably noisy) ground.

Thats what they done in the reference layout. There is no direct connection to another groundplane on this side of the IC, it just connects to PGND over the exposed pad underneath