Buffert driver has better rail-rail performance then an MCU?

[implor]

I'm reading a application note/article about PWM filtering to DC.

there they have this statement:

Because the peak-to-peak PWM signal value directly
appears in the resolution (Equation 4), it is highly desirable to get this value as stable as possible. This value is a
combination of the supply-voltage accuracy and the driver’s voltage-high and voltage-low accuracy. The accuracy
and stability of these parameters are poor for MCU
general-purpose inputs/outputs.
A simple solution is to buffer the MCU PWM output with
low-power high-speed logic gates, which would also be
required to invert signals required by active ripple
suppression. Powering logic gates with a stable voltage
reference instead of a typical power device leads to very
accurate and stable signal generation.

They suggest SN74LVC2G240 in the diagrams.
https://www.ti.com/product/SN74LVC2G240?qgpn=sn74lvc2g240


But my question is is this really true?

Normal LDO have +/- 1% regulation and MCU can go pretty close to VDD.
So i would think the buffer might be slightly better but not a massive improvement? Or am I wrong?

Article i'm reading:
https://www.ti.com/lit/an/slyt795/slyt795.pdf?ts=1760866522066&ref_url=https%253A%252F%252Fwww.google.com%252F

[voltsandjolts]

External buffer and voltage reference sound like good enhancements, but whether you need them in your application depends on your requirements for stability, accuracy, resolution, tempco, etc.

[Ian.M]

... which would also be required to invert signals required by active ripple
suppression ...

The EDN ripple cancellation article by S. Woodward that some of that AN was based on is no good.  See https://www.eevblog.com/forum/metrology/pwm-new-article-from-s-woodward/

[mtwieg]

A driver with a CMOS output stage would be best (as opposed to a TTL output, for example). Practically all MCU's will have CMOS outputs already.

Also one should keep the loading on the driver very light, such that its output devices are always operating as small resistors. For example, for LVC logic you would want to limit peak load current to <5mA.

So a MCU output could work just as well as an external logic device (assuming both have the same supply voltage tolerance). Using an external logic device means you don't have to power the entire MCU from a reference voltage, though.

But if you're really after accuracy on the order of 1%, I wouldn't be considering filtered PWM in the first place...

[MariuszD]

The MCU has a decent output stage, consisting of MOSFETs, but the power supply circuits inside the MCU power many different blocks, voltage drops can occur on the internal power lines, and there are noise sources inside.

[Doctorandus_P]

It all depends on what your goals are. If you want to control an LED with some PWM, then it does not matter, but if you want to achieve the highest resolution, accuracy, precision, etc possible then all small details matter. Back in the '80-ies there were voltage reference generators / calibrators that used PWM techniques and achieved 20 bits or more of resolution. It's also a topic that I'm interested in because quite good results can be achieved with a low BOM cost.

First thing would be to use a better voltage reference. You can power the uC from such a voltage reference, but there is lots of stuff going on in a microcontroller, and only using the voltage reference to power the external buffer IC both lowers the current load from the reference, and reduces all the noise generated by the uC from the PWM signal.

Whether the output of an uC is "better" then a single output from a (CMOS) TTL IC depends on both the uC used, and which TTL family. Both use an P-channel fet to switch to power rails and a N-channel Fet to switch to GND, and these switches are not ideal. There will be asymmetry, and their channel resistance is also temperature dependent. With an TTL IC you can parallel up a bunch of outputs, which reduces the output impedance relative to the PWM filter used. And a TTL buffer is cheap, so why not? If you use a DIP package, you can even stack 2 or more IC's on top of each other for paralleling more channels.

Maybe better results can be achieved with a gate driver IC. These are designed to deliver high peak currents, and thus have FET's with a small channel resistance.
Another option is to make an output buffer from 2 fets yourself. That way you can balance their properties, and even hand sort them (although that's not good for a production environment). They should also be thermally coupled (or at least close to each other) so temperature effects on the channel resistance is similar for both FET's.


EDN is already mentioned, but they have more. They have a whole series of articles about PWM + Filtering to get to DC.

[PGPG]

So i would think the buffer might be slightly better but not a massive improvement? Or am I wrong?

I have opened used by us AtXmega datasheet and Diodes LVC1G17 datasheet.
Both have outputs specified when supplied by 3V.
Vol max for uC is 0.64V/10mA while for LVC is 0.4V for 16mA. You can simplify MOS output assuming it has specific resistance so for output low uC R is max 64Ω and for LVC it is max 25Ω.
Voh: uC is 2.1V/6mA and LVC 2.4V/16mA. From that I get uC R=150Ω and LVC R=37.5Ω.

My conclusion: For Vol LVC is 2.5 times better. For Voh LVC is 4 times better.

[iMo]

When the Vcc/gnd for the external buffer is "independent of the MCU one" and good filtered/stable then also the noise/jitter off the buffer's output will be "much" lower than the output from the usually noisy MCU, imho..

[mawyatt]

EDN is already mentioned, but they have more. They have a whole series of articles about PWM + Filtering to get to DC.

We posted something in EDN back in 1989 about using CMOS for a precision DC voltage divider.

Here's some links about using CMOS Logic for creating precision analog results.

https://www.eevblog.com/forum/projects/fun-circuit-to-play-with/

And one about using a CMOS squarewave to create a precise RMS waveform.

https://www.eevblog.com/forum/testgear/ac-rms-dmm-tests/

This created some controversy as you can read, however we'll stand by our comments/statements and results, as over the years it just works and works quite well indeed for us as shown below (VDC Ref is 5.000904VDC, AC RMS is 2.500027VRMS)   

As always, YMMV

Best

[mawyatt]

WRT the typical CMOS output stage. The Low Level is set by the NMOS while the High Level is set by the PMOS. The PMOS is usually 2~4X time more area than the NMOS to make up for the lower NMOS Rdson, but usually doesn't quite make up the difference, so the low side is often a lower resistance.

Best

[David Hess]

But my question is is this really true?

Normal LDO have +/- 1% regulation and MCU can go pretty close to VDD.
So i would think the buffer might be slightly better but not a massive improvement? Or am I wrong?

Complex ICs like an MCU or FPGA have a lot of circuits other than the output driver drawing current through the supply and ground connections, so the internal supply voltage and ground are not as stable as a logic gate on a simple IC.

Also, CMOS logic thresholds follow the supply and ground voltages, so an output driver also has added jitter.  In a precision application, this might be removed by reclocking the output from the complex logic, or using external logic for PWM generation.

[PCB.Wiz]

But my question is is this really true?

yes.

Normal LDO have +/- 1% regulation and MCU can go pretty close to VDD.

If 'pretty close' is the only spec you have to meet, then sure, 'have a go'. 

So i would think the buffer might be slightly better but not a massive improvement? Or am I wrong?

That depends on how bad the MCU is, and how busy it is.
Some have very poor VOH noise & crosstalk, as they focus more on ground metal than VDD metal when designing the die.
Some I've seen could be as bad as 5 bits of usable PWM precision.

A separate buffer lets you use a precision reference with only the PWM load.
You can also use SPDT analog switches, which can give lower Ron than CMOS gates.

[mawyatt]

A separate buffer lets you use a precision reference with only the PWM load.
You can also use SPDT analog switches, which can give lower Ron than CMOS gates.

This is a good solution as it allows the use of a precision reference (5.000V for example) if desired.

WRT the CMOS gate vs analog switch, the gates are faster and can have very "low effective" output resistance and paralleled for even lower output resistance. The analog switches are optimized for a good "linearity" across the input voltage range, which isn't important for this type PWM application, whereas the application only "cares" about the high and low output values.

If one decides to use a CMOS gate(s), you can easily establish the output resistance in the High and Low state by just sinking a small current when the gate is constant low and measure the voltage drop to ground, and do a similar approach sourcing a current with the gate high and measure the voltage to VDD. If the need requires even lower values then a discrete CMOS inverter with a discrete NMOS and PMOS can be used like we did in our AC RMS Reference mentioned earlier. For example, we used a 2N7002 and BSS84 for an Rdson of ~3Ω.

There's always a trade off with speed to consider, and some of the newer logic gates have very low output resistance and are very fast. One thing we've wanted to try was utilizing a very fast CMOS gate and "equalize" the NMOS and PMOS Rdson by adding a small resistor in the package ground lead for use with the ppm Precision Voltage Divider also mentioned earlier.

Anyway, applying CMOS logic gates for precision analog use was an interesting endeavor for us way back and still quite interesting

Best 

[implor]

Thank for excellent input everyone!

I will try using an analog switch connected to GND and Vref. It sound simple and reliable (and worked fine when i simulated in Tina). Especially when it's only 1khz PWM.

mawyatt post was very interesting. Can't say I really understand it but I will try to find time to simulate it some time soon. Would be interesting if this would be cheaper then a similar spec. reference.

[mawyatt]

mawyatt post was very interesting. Can't say I really understand it but I will try to find time to simulate it some time soon. Would be interesting if this would be cheaper then a similar spec. reference.

The CMOS Analog Switch is optimized for linearity across the analog input voltage range (say 0 to 5 volts). The CMOS Gates are optimized for Speed and Low Output impedance at a 0 (Vss) and 1 (Vdd) output. The faster CMOS gates have a low output impedance to drive the output capacitance quickly, and are ideal for PWM applications, and are cheap!!

Best

[implor]

So something like SN74LVC1G08 would do?

I will order parts and hack something together before next board revision so I tough just test both.

[PCB.Wiz]

So something like SN74LVC1G08 would do?

Yes, check the drive, you may find buffers like 74lvc1g126 have lower resistance in a similar package.

You can also get SPDT switches down to sub 1 ohm.
Check the speeds on those, there are two broad groups.
Those designed for level shift and lowest icc can be slower, than the switches not targeting that feature.

[Terry Bites]

www.analog.com/en/resources/technical-articles/op-amp-precision-positive-negative-clipper-using-lt6015-lt6016-lt6017.html