Circuit help - digital output driver

[c4757p]

OK, I'm pretty far out of my areas of experience, so I'm kind of just poking around in the dark here. I'd like to build myself a pulse generator. Requirements are: can output up to 10V into 50 Ohm load or 20V into high impedance, rise time around 10ns (faster would be great!), digitally driven input (coming from a CPLD to allow somewhat complex pulse patterns - I plan to couple this to SRAM to allow externally defined patterns as well).

I really have no idea how the output buffer for something like this would usually be designed, and I can't find too much information on it, so I took a shot at designing one. This is only in LTspice, mainly because my bench is currently packed full with the test setup for a SMPS and this circuit's too complicated to test crammed into a little corner of the bench...

Here's what I have. I was hoping someone who is knowledgeable in this area can provide a few suggestions. ("This circuit's stupid and you should throw it out" is perfectly valid  ) I've got a few questions:

1) Some of the capacitances seem pretty finicky (particularly C2). I really don't want trimmer caps in a digital circuit, but it doesn't run nearly fast enough without them. Can they be eliminated somehow?
2) Schottky diodes D7 and D8 clamp the output voltage to just shy of the rails. That's fine on the positive rail, but can the negative rail be made to go closer to ground? Removing them makes the output transistors as slow as molasses in January.
3) The lowest reasonable positive rail is 5V, giving just under 2.5V into 50ohm. 4V works, but the falling edges come too early and mess up the waveform a bit. Under 4V doesn't work. Any obvious way to lower this? I'd like to be able to go down to 1.8V into 50ohm, or lower if possible.

Edit: Tweaked a couple values in the SPICE file for better performance. No change to screenshot.

[c4757p]

Anyone? Sorry, I don't mean to "demand" help, but I have literally no experience with the discrete semiconductor side of digital electronics and I'm really hoping someone can help me out. I'm having a tough time making a driver that's fast and regular, but also has a wide range of output voltages.

[marshallh]

Something that came to mind was using a FET driver.

http://www.digikey.com/product-detail/en/MCP1416T-E%2FOT/MCP1416T-E%2FOTCT-ND/1963940

Wades through 1000pf gate capacitance (or cable capacitance) in under 20 seconds,
1.5A output current, supply it with up to 18 volts. That should be sufficient for your worst case of 10V into 50ohm

Typical switching time is 20ns. Not quite fast enough, you could look around harder or check out other types of output drivers

http://ww1.microchip.com/downloads/en/DeviceDoc/22092E.pdf

[croberts]

Operating the output stage with all transistors always biased on (like the buffer stage) would yield more speed and then use an adjustable offset and gain for the desired output voltage swing and level.

[c4757p]

Good point. I'll have to investigate how to control the gain for a predictable output voltage without sacrificing speed, but that shouldn't be too hard. (Or use fixed gain and variable attenuation of the input.) Sucks that digipots have such shitty bandwidth...

[codeboy2k]

I was doing some simulations yesterday on your circuit but didn't come up with anything useful yet...

I changed the input stage to an ac coupled NFET with a BJT comparator on it's output.. this is your BUF node. I went this route because I wanted to create an input buffer that has a consistent drive voltage output no matter what the input voltage is.  I wanted this because your input stage is a class AB amplifier, and it is input voltage sensitive, but I wanted to avoid that sensitivity to varying input voltages.  I wanted a fixed output level from the buffer stage to the driver stage.

The final goal was to have a driver stage that was always biased on, never in saturation, and could switch faster using a known, fixed input control signal (your BUF input to the driver) ... I got busy on other stuff and didn't finish with enough information to post here.

[vlf3]

It's no that easy to design complimentary B class amps, with 10ns rise; so you are in for a challenge then... 

My limited experience would place this design in the RF area, where class B or A/B is border line upto 1Mhz; normally for greater bandwidth using two transistors, a cascode transistor design would suffice, however more transistors equate to more junction capacitance, thus keeping the transistor numbers down would help that aspect, even so, C class would provide a liner rise time if biased before saturation point but, you need to burn some current to achieve that, with a high frequency device.

To the point; here is a circuit with a difference mainly, it's largely formed by emitter follower's producing high impedance input interface to a logic gate; this might be the better approach ?... go down the page to see the circuit:

http://www.next.gr/rf/amplifiers/five-transistor-amplifier-l12008.html

Also here is a pdf down-load for an RF chip amplifier NE592 for under $0.50, that might provide some food for thought...

http://www.qsl.net/zl1wtt/pdf/NE592.pdf

[free_electron]

just add a pin driver and you are done.
you will be able to set high and low level independently , limit the current and more stuff.

EL1065
AD53040
EL7154

for example. these things drive 500Mhz 20 volts into 50 ohm without blinking...

google for 'ATE PIN DRIVER'

these chips are used in big industrial testers like Teradyne , Agilent , Advantest and others (we're not talking homebrew racks with some gpib instrumentation but dedicated machinery to test integrated circuits )

they have one of these drivers per 'pin' of the device under test. the advanced pin drivers can switch analog and digitial , and you can readback voltage and current going to the pin. they are virtually indestructable.

they are not cheap... think 20 to 30$ for  a device , but ... you have no hassle with all that discrete muckery. these things simply work.

[free_electron]

some vendors that have a wide portfolio of such things :

http://www.intersil.com/en/products/end-market-specific/ate-ics.html
http://www.analog.com/en/other-products/automatic-test-equipment/products/index.html
http://www.maximintegrated.com/datasheet/index.mvp/id/4401
http://www.ti.com/lit/ds/symlink/buf634.pdf
http://www.semtech.com/Press-Releases/2006/Semtech-debuts-high-speed-pin-electronics-driver-for-next-generation-memory-testers.html

[c4757p]

Those are impressive chips, I'll definitely check them out.  Still, this is just a hobby project - I'd rather use things I already have available if I can.

[c4757p]

I was doing some simulations yesterday on your circuit but didn't come up with anything useful yet...

The current version seems somewhat decent. I can probably get the minimum voltage down a bit with some adjustments to biasing, and the rise and fall time are both acceptable. I don't like the output low voltage around 0.1V, but I may be able to solve that just by biasing the low output section a bit negative.

I changed the input stage to an ac coupled NFET with a BJT comparator on it's output..

No AC coupling, unless I misunderstand what you're saying. A pulse generator like this should be configurable to give (e.g.) a 100ns pulse every ten seconds or something ridiculous like that - you'd need one real mother of a capacitor to AC couple a 10s signal...

Thanks for looking into it!

[c4757p]

It's no that easy to design complimentary B class amps, with 10ns rise; so you are in for a challenge then... 

You're not kidding! 

C class would provide a liner rise time if biased before saturation point but, you need to burn some current to achieve that, with a high frequency device.

I have no problem with burning some current in this circuit!

To the point; here is a circuit with a difference mainly, it's largely formed by emitter follower's producing high impedance input interface to a logic gate; this might be the better approach ?... go down the page to see the circuit:

http://www.next.gr/rf/amplifiers/five-transistor-amplifier-l12008.html

I like that.

Also here is a pdf down-load for an RF chip amplifier NE592 for under $0.50, that might provide some food for thought...

http://www.qsl.net/zl1wtt/pdf/NE592.pdf

Whether or not that ends up being useful here, it looks good as a general chip to keep in mind. Thanks!

[c4757p]

Just have to finish tweaking this damn SMPS that's taking up my whole bench and I'll actually poke around with this in real life..

[c4757p]

Built and tested. Everything but the pull-down section works admirably - I had a beautiful 6 ns rise to 7.5V with no visible ringing into 50 ohm (I wasn't thinking too much when I prepared the test setup, and 15V input was the greatest I could give it, so no 10V output test). The falling edge was a different story. It ended up having two trimpots (the two bias voltages, +1 and -1 in the sim, ended up being adjustable), and the big old "fail!" is that the proper settings for the trimpots varied with output voltage.  Can't have a little oompa-loompa in there tweaking the trimmers as the voltage changes, can we?  So I'll scrap and redesign the pull-down section and respin the prototype (I wasn't about to do 10ns on a breadboard, so I did a PCB). Hopefully #2 works.

(And, a PSA: If you're trying to look at a 10 MHz square wave, for God's sake make sure the bandwidth limiter is off before you think your circuit's broken...)

[c4757p]

Fixed the wonky bias voltages by adjusting a couple component values - NBD. Something was being starved of current at some V+/bias combinations and just needed a lower resistor. (Side note: Am I the only one who instinctively thinks of lower value resistors as "larger" resistors because they're bigger loads? Had to catch myself there...)

Next problem is that because the signal path through the upper section inverts twice, and the signal path through the lower section inverts just once, the propagation delay through the two halves is slightly different, leading to the high and low drivers fighting each other during the falling edge. I'll see if I can get a single transistor biased to give both inverted and non-inverted outputs (and still operate fast) to solve the delay problem.

Follow-up: Quite easy to get inverted and non-inverted signals, even at that speed, if I'm willing to burn 200mA to do it! The old "equal emitter and collector resistors" trick only seems to work well in this case with absolutely tiny resistors. Oh well...

[vlf3]

I knew you would get there, with a bit of technical re-engineering; well done. 

[fmaimon]

Try using figure 101 from Jim Williams AN47, although it won't go much near ground.

[c4757p]

Hard to argue with Jim Williams - except on the basis of "I'm almost done and it's working fine!" 

[c4757p]

although it won't go much near ground.

That would be a deal breaker, though with the -15V rail in there, I doubt that.

[fmaimon]

although it won't go much near ground.

That would be a deal breaker, though with the -15V rail in there, I doubt that.

That was assuming you don't have a -15V rail, as digital is usually ground and, say, 5V. But checking your spice file, you are using a -5V rail, so you should be good.

[c4757p]

Yeah, I was having trouble yanking the output down to ground fast enough without having something below that.

I've actually completely redesigned it now, but I don't have a file for it, it's just pen and paper right now. I'm getting much better edges (falling especially) by separating the voltage gain stage from the output driver.

[c4757p]

The voltage amplification stage is complete. My suspicions about it being crap on a breadboard were, of course, correct (a quick calculation gives about 60nH ground inductance in one particular spot being enough to completely screw up the waveform, and screw up the waveform it did), so I soldered it freehand to a copper plane. Only thing left to do now is the output drive stage (piece of cake) and spin a PCB.

I was a bit flexible on the rise/fall - I'm getting around 13ns, and I'm OK with that. Perhaps on a well-designed PCB with higher bandwidth/gain transistors (I'm using common 2N3904 here) and tightly spaced SMD parts the same circuit can perform a bit better. I was also a bit careless with probing when I took those measurements, so I guess we'll see what the final output is when it's a straight shot through from 50 ohm input to 50 ohm output.

Some pics here if anyone cares to look.

No schematic at this point - I had one, but made a bunch of changes directly to the circuit, so it doesn't match anymore. I'll recapture it when I have the whole thing 100% complete.

If anyone notices on the scope - yes, the duty cycle is off a bit. This is caused by the bias being just a bit low at one point, combined with the input waveform actually being a sinusoid (my function generator has double the max frequency on sine, and the circuit doesn't give a rat's ass what the input looks like) - when I actually build this, I'll put in a trimmer, but here I was just swapping out resistors.

[c4757p]

Tentative schematic attached, PCB later tonight.

[c4757p]

PCB, also tentative. I'm sure I'll realize it's completely wrong after some sleep and some coffee...

[c4757p]

Finally received and assembled my PCBs. God, that was probably the longest I've waited for PCBs ever. But I'm happy. 

Notes, thoughts and goofs:

- 3ns rise! (At low voltages - seems to be limited by approximately a 2V/ns slew rate.) Much better than the original goal.
- Addendum: of course the rise time is good (and limited like that) - it's just an RC constant... The fall time is the important one, and it's even better!
- Bit of bouncing around after the falling edge. 1. In the 2V and 7V captures, this is worse than reality; the level shifter (RV1, R5, D1-D4 in the schematic) was biased wrong. It gets much better. 2. It gets worse again around 8.5V, as is obvious in the 9V capture with correct bias. I may limit the output voltage to 8V. 3. May be related to improper termination on the lower output transistor (Q8). I didn't have a 3.3 ohm resistor so I used a 0R link. But I don't think 3 ohms worth of termination error will cause much difficulty even at 3ns.
- The level shifter has a slight error - it's impossible to bias it perfectly; the signal is lost right before correct bias is achieved. At high frequencies there's either a slight duty cycle error (as seen in the 9V capture - it's a slight delay in the rising edge) or some nastiness on the falling edge. I'll take the duty cycle error; it's not too bad.
- Soldering isn't the best, but with 40-something 0805 capacitors per board I don't care. It works.
- I dated the board "2012" accidentally.  I've been doing this all year...
- I'm rather proud of that nearly unbroken ground plane.