Compensation for buck error amplifier at less than full load?

[kimballa]

I'm working on the design of a class D amplifier and I am stuck on a question about the DC regulator. The amp will need a fair bit of power (~100W / channel); I have a separate Ac/DC converter that will provide plenty of power at 36V, but the amp IC (TPA3245) wants 30V nominal, not to exceed 31.5V.

To provide this, I'm designing a 36->30V buck regulator around the TPS40200 controller and an external FET. The design parameters are for a steady state max of 12A out at 30V (360W), tolerating transient surge / overcurrent conditions up to 15A out. So far so good - I have a low-rds FET, inductor, diode, and output capacitors chosen.

Designing the compensation network for the error amplifier, however, is a head-scratcher because it requires factoring in the R_load into the equation.

I can design easily enough for either the steady state max (12A@30V = 2.5 ohms) or surge max (2 ohms), but in practice most of the time my speakers won't be operating even remotely close to full power; this needs to be stable at 2W load too (450 ohm R_load).

How does this work? I have scoured the net and cannot find any discussion of regulator stability under varying load.

The closest thing is TI app note slva301, which discusses characterizing Bode plots for a voltage mode controller operating under both CCM and DCM conditions, as well as at the critical transition current between the two, but I don't see from there how to make the compensation network operate over two decades of load impedance.

If you design the compensation network for max load current, does that just automatically mean any lower current surges are handled in an overdamped fashion and it works "fine"?

Or assuming it's also designed for the max load (which I did), does the output bulk capacitor (I have 4x270uF, 1080uF total) just swamp any smaller load demands and you don't have to worry?

The class D amp does not specify a PSRR for the output power VDD, so I assume that at any max volume (say 1W, or 10W), a sudden transition from soft to loud in the audio signal will cause a small demand spike on the power, which if left uncorrected by bulk capacitors or the regulator, could cause ripple on the output voltage and thus induce distortion.

[mtwieg]

Often varying load isn't much of an issue for compensating a buck converter. There's a couple reasons for this:
1. There's no RHPZ for a buck converter (for a boost or buckboost, the RHPZ frequency shifts with the load).
2. As the load decreases, the buck will transition from CCM to DCM. If it was stable in CCM, then it's practically guaranteed to be stable in DCM.

However #2 isn't true if you have a synchronous rectifier and operate in forced CCM rather than allowing for DCM. In this case, you may have problems at light load if the Q of your output LC filter is high. In this case I would intentionally reduce the Q by adding some damping to the LC filter. Easiest way to do so is add a series RC in parallel with the existing filter cap. The new C should be ~3x the original, and R should be around sqrt(L/C). This will ensure a low Q (better stability) even with no load.

[temperance]

Are you sure the TPS40200 will do the job? The gate drive can supply 200 mA, and you want a buck power stage capable of supplying transients in the neighbourhood of 12 A. A capable MOSFET, >60 V and 18 A, will have a gate charge (miller plateau, switching charge) around 20...40 nC.

[kimballa]

I believe so? For a FET I was planning on using Goford GT065P06T. 62nC Qg, and 8mOhm rds,on. Even at 20A, the DC loss is only 3.2W. AC loss adds about that much again, but it seems like it's in the range of what a decent heatsink can handle...

[kimballa]

Often varying load isn't much of an issue for compensating a buck converter. There's a couple reasons for this:
1. There's no RHPZ for a buck converter (for a boost or buckboost, the RHPZ frequency shifts with the load).
2. As the load decreases, the buck will transition from CCM to DCM. If it was stable in CCM, then it's practically guaranteed to be stable in DCM.

However #2 isn't true if you have a synchronous rectifier and operate in forced CCM rather than allowing for DCM. In this case, you may have problems at light load if the Q of your output LC filter is high. In this case I would intentionally reduce the Q by adding some damping to the LC filter. Easiest way to do so is add a series RC in parallel with the existing filter cap. The new C should be ~3x the original, and R should be around sqrt(L/C). This will ensure a low Q (better stability) even with no load.

Thanks mtwieg, that explanation makes sense. This is a non-synchronous design so it sounds like we're good here.

[MariuszD]

I can design easily enough for either the steady state max (12A@30V = 2.5 ohms) or surge max (2 ohms), but in practice most of the time my speakers won't be operating even remotely close to full power; this needs to be stable at 2W load too (450 ohm R_load).

A Class D amplifier with feedback does not behave like a resistor. When the supply voltage increases, the current decreases, so the converter load is a negative resistance. Negative resistance can increase the quality factor of the LC circuit or cause instability. That's my thought but I don't know if it's a real problem. I would like to see what others think about this.

[kimballa]

A Class D amplifier with feedback does not behave like a resistor. When the supply voltage increases, the current decreases, so the converter load is a negative resistance. Negative resistance can increase the quality factor of the LC circuit or cause instability. That's my thought but I don't know if it's a real problem. I would like to see what others think about this.

Does this also apply to dual amplifier-per-speaker configured as bridge-tied loads? Or only for single-ended amplifier loads?

[Someone]

A Class D amplifier with feedback does not behave like a resistor. When the supply voltage increases, the current decreases, so the converter load is a negative resistance. Negative resistance can increase the quality factor of the LC circuit or cause instability. That's my thought but I don't know if it's a real problem. I would like to see what others think about this.

Does this also apply to dual amplifier-per-speaker configured as bridge-tied loads? Or only for single-ended amplifier loads?

Either. Class D amplifier is basically a buck regulator its self.

[mtwieg]

A Class D amplifier with feedback does not behave like a resistor. When the supply voltage increases, the current decreases, so the converter load is a negative resistance. Negative resistance can increase the quality factor of the LC circuit or cause instability. That's my thought but I don't know if it's a real problem. I would like to see what others think about this.

Yeah also important to keep in mind that it's rare for the load on a power supply to actually behave like a resistor equal to Vload/Iload. If the load is a power circuit with its own feedback loop, then it will appear as a negative resistance load. At least that's the case at low frequencies (as  frequency increases, the real part of the load impedance tends to become positive again).

Again, adding damping networks can make these issues a lot easier to deal with.

Does this also apply to dual amplifier-per-speaker configured as bridge-tied loads? Or only for single-ended amplifier loads?

It doesn't matter how the amplifier's load is configured. The point is, if that amplifier has a regulated output (i.e. it has negative feedback from its output which allows it maintain the same output voltage/current in the presence of supply voltage variation), then it will behave as a constant power load. Constant power loads behave as a negative resistance (if you raise supply voltage, load current will go down).

[temperance]

I believe so? For a FET I was planning on using Goford GT065P06T. 62nC Qg, and 8mOhm rds,on. Even at 20A, the DC loss is only 3.2W. AC loss adds about that much again, but it seems like it's in the range of what a decent heatsink can handle...

20 nC with 200 mA drive current means the switching times will be around 100 ns. The power dissipation is roughly equal to 0.5 x Vin x Id x (Trise + Tfall) x (switching frequency).

[kimballa]

20 nC with 200 mA drive current means the switching times will be around 100 ns. The power dissipation is roughly equal to 0.5 x Vin x Id x (Trise + Tfall) x (switching frequency).

Hmm -- I'm afraid I don't understand how to reconcile these figures with the TPS40200 datasheet (https://www.ti.com/lit/ds/symlink/tps40200.pdf). Can you point out what I'm misunderstanding?

On page 21 it says the gate current is I_G = Q_G × f_S. My switching frequency is configured at 290 kHz. At Q_G = 62nC, that's only 18mA, which is well within the abilities of the gate driver.

On the same page, equation 10 gives the turn-on time t_CHON = (Q_GD * R_G) / (VIN - VTH), t_CHOFF is the same but with VIN as the denominator.

The Q_GD is 16.8nC, I have chosen R_G of 10 ohm (the TPS40200 does not specify any internal R_G), VIN is 36V, VTH is 1.7V; that gives an improbably fast switching time t_CHON of 4.67ns. The FET datasheet, however, says the turn-on rise time t_r is 18ns. t_f is quoted as 35ns.

P_SW = 1/2 f_s * VIN * I_pk * t_CHON + 1/2 f_s * VIN * I_pk * t_CHOFF.

With peak current I_pk of 15A, and taking the slower t_r / t_f values from the datasheet (18 & 35ns), that gives a super-manageable 4.135W.

That said... Equation 4 from an article I found, "MOSFET power losses and how they affect power-supply efficiency" (https://www.ti.com/lit/an/slyt664/slyt664.pdf) gives a different formula for P_SW. It relies on one figure from the datasheet parametric table (Q_GD) and requires inferring another (Q_GS2) from one of the graphs (I make it ~4.3nC).

P_SW = V_DS * I_OUT * f_s * (Q_GS2 + Q_GD)/I_G

If you take V_DS as the full VIN (36V to GND), and assuming the full 200mA sink from the gate driver, this gives P_SW = 16.5W, which is more in line with the figure you were warning about.

But the source is at 36V (VIN) and the drain is connected via the inductor to the load. (This is a high-side P-MOSFET.) Assuming the regulator is doing its thing, the load is at 30V. So... what voltage do we use at the drain?

* If the drain is at 30V, then V_DS is 6V (ignoring the inductor DCR for the moment), that's 2.74W -- which is much closer to the calculation from the datasheet equation.
* If the FET is completely off, then the drain is at 0V (the inductor having snapped negative and the freewheeling diode keeping it essentially grounded)
* If the FET is completely on, then the drain is at V_IN - r_ds(on) * I_load = 36 - 0.008 * 15 = 35.88V.

Assuming CCM, the inductor is essentially a short, and the average drain voltage should be the regulated load voltage (30V), so thus we use that (V_DS = 6V), right?

[temperance]

On page 21 it says the gate current is I_G = Q_G × f_S. My switching frequency is configured at 290 kHz. At Q_G = 62nC, that's only 18mA, which is well within the abilities of the gate driver.

This is correct and represents the equivalent DC current going into the MOSFET driver part of the IC.

The Q_GD is 16.8nC, I have chosen R_G of 10 ohm (the TPS40200 does not specify any internal R_G), VIN is 36V, VTH is 1.7V; that gives an improbably fast switching time t_CHON of 4.67ns. The FET datasheet, however, says the turn-on rise time t_r is 18ns. t_f is quoted as 35ns.

This is not correct. Q_GD is much larger. See sig. 6 in the data sheet. The horizontal part of the graph is around 20 nC. This is the amount of charge required to drive the MOSFET into saturation.

https://www.gofordsemi.com/upload/cn/propdf/GT065P06T.pdf

The app note you've linked to, fig 5 and the text referencing fig 5 explain in detail how this works:
https://www.ti.com/lit/an/slyt664/slyt664.pdf

You can try boosting the output current of the MOSFET driver with a totem pole buffer and some jelly bean transistors.

[temperance]

Assuming CCM, the inductor is essentially a short, and the average drain voltage should be the regulated load voltage (30V), so thus we use that (V_DS = 6V), right?

Yes, that's correct.

[kimballa]

Assuming CCM, the inductor is essentially a short, and the average drain voltage should be the regulated load voltage (30V), so thus we use that (V_DS = 6V), right?

Yes, that's correct.

OK, using the app note formula, VIN=VDS=6V, the other variables I mentioned, and the Q_GS2, Q_GD from the graph in the datasheet, I get 2.76W of switching power dissipation. I think that's right?

Thanks for the help

[temperance]

VIN=VDS=6V

You must calculate the dissipation using Vin, the real input voltage of the buck regulator. This is what the MOSFET sees every switching cycle when the buck converter is working in CCM mode because the inductor is clamped by a diode to GND.

Edit: modified my explanation because it didn't explicitly state the drain source voltage.

[NiHaoMike]

Have you considered moving up to a higher end amp chip like the TPA3255 which can run from 36V directly?

[kimballa]

Have you considered moving up to a higher end amp chip like the TPA3255 which can run from 36V directly?

That's actually pretty inspired. It's inexplicably cheaper at Digikey than the '3245, too.