Author Topic: Controlled symetric slew rate limiter  (Read 2359 times)

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Offline jeduffyTopic starter

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Controlled symetric slew rate limiter
« on: February 26, 2025, 06:12:36 pm »
Does anyone know of a reference design or good general method for very controlled and symmetric slew rate limiting?
Effectively I want to take a square wave in with very fast (<<1uS) edges in, and put out as close to a perfect trapezoidal wave as possible, with very linear slopes, both up and down, very little overshoot, oscillation, etc. 

The slew rates I'm looking for are on the order of maybe 1-10V/uS, the exact value of the rate doesn't matter, only the matching between the up and down rates, preferably without requiring any matched resistors, transistors, etc. 

Also just because that's not enough, the DC accuracy once it gets to the extremes should be well within a uV of the input signal (I can use a chopper amp with sufficient performance for the input stage). 

If an opamp perfectly obeyed the maximum slew rate settings, theoretically I could just use an amp with a very slow slew rate, but I don't necessarily trust that they'll actually be as slow as I want (often they just give a typical value), or particularly linear (may look more like an RC circuit).

In theory a simple bidirectional current limiter at the output of an opamp, into a capacitor should solve this problem, but I'm not aware of a good design for something like that either.

I did find a TI app note that uses a pair of inverting amplifiers, but I have had a few problems implementing it in simulation without overshoot, ringing, and instability.

Thanks!
 

Online moffy

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Re: Controlled symetric slew rate limiter
« Reply #1 on: February 26, 2025, 08:45:20 pm »
With such stringent demands of uV accuracy, a settling time, voltage swing and probably frequency of the square wave are important to know. A chopper amplifier while having good DC accuracy and drift doesn't have the best dynamic performance or BW.
« Last Edit: February 26, 2025, 09:59:18 pm by moffy »
 

Offline 741

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Re: Controlled symetric slew rate limiter
« Reply #2 on: February 26, 2025, 09:03:28 pm »
Can a standard op-amp integrator type "triangle wave generator" design be adapted I wonder?

Once a triangle wave exists, there must be a neat way to flatten the top portion ... (?)

Maybe diodes across the capacitor, but for symmetry, the exact same diode somehow switched around and acting in reverse for a falling edge.

Offline Doctorandus_P

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Re: Controlled symetric slew rate limiter
« Reply #3 on: February 27, 2025, 02:07:08 am »
An opamp configured as an integrator is probably the most standard method, especially if linearity of the ramps is important. Simpler / cheaper is to use a push pull stage, and add two miller capacitors.

For DC accuracy into the micro Volts, there are some famous filters from old HP equipment. It's basically an opamp based filter win which both the input and output of the signal are coupled AC into the signal. So whatever the filter does, it's effect on DC output is negligible.

I do not know what the final goal of this circuit is. If you want to for example take a PWM signal and filter it to DC, then any twiddling with the ramps would be very critical. I guess that in that case, it's probably better to get those ramps over as quickly as possible (i.e. no slew rate limiting) and then use an appropriate filter afterward. But any circuit is a tradeoff between a lot of different goals, from part costs to accuracy, and advise to such a generic question will also be pretty generic.
 

Online PCB.Wiz

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Re: Controlled symetric slew rate limiter
« Reply #4 on: February 27, 2025, 02:22:06 am »
Does anyone know of a reference design or good general method for very controlled and symmetric slew rate limiting?
Effectively I want to take a square wave in with very fast (<<1uS) edges in, and put out as close to a perfect trapezoidal wave as possible, with very linear slopes, both up and down, very little overshoot, oscillation, etc. 
...
In theory a simple bidirectional current limiter at the output of an opamp, into a capacitor should solve this problem, but I'm not aware of a good design for something like that either.
The challenge with bidirectional current would be matching the two directions.

If you want 1-10V/us the simplest here is likely to create a variable symmetric DC voltage, that is analog switched +/- into a single integrator/cap.
That will be as balanced as two opamp outputs  ie to resistor precisions 0.1% etc, and a separate low pass DC loop feedback can keep DC average very low.

It will naturally clip at the rails, if you want to keep DC, you need to ensure your square wave is 50.00% duty cycle and the opamp clips symmetric.

Some recovery overshoot from clip will be inevitable, you could trade off feedback clipping (softer tops) for better response.



 

Offline RoGeorge

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Re: Controlled symetric slew rate limiter
« Reply #5 on: February 27, 2025, 08:10:05 am »
See if these help:
https://www.ti.com/lit/an/sboa218b/sboa218b.pdf?ts=1731566730893
https://www.ti.com/lit/ug/tidu026/tidu026.pdf?ts=1731542141599

There were a few threads here on EEVblog.com, where you might find more hints or links.  Search for appropriate terms, and limit the search results to eevblog.com only, by using site:eevblog.com like this
slew rate design site:eevblog.com
https://duckduckgo.com/?q=slew+rate+design+site%3Aeevblog.com&t=ffab&ia=web
 
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Offline Jay_Diddy_B

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Re: Controlled symetric slew rate limiter
« Reply #6 on: March 01, 2025, 03:39:04 pm »
Hi,

Let me share this schematic. It generates a reasonable approximation to the OPs requirements. The circuit uses a few analog design 'tricks'.

Concept



There are two current sources that determine the positive and negative slew rates. These are switched into a capacitor using Schottky diode switches. There are clamping circuits that set the positive and negative amplitude. Additional diodes are operated at the same currents. The diodes should be matched and thermally coupled.

The op-amp in this circuit is not required to slew. The voltage on the output is constant. Low frequency precision op-amps can be used.

Practical Circuit

This is a practical circuit, showing the waveforms:






There are voltage sources that set the slew rate, positive level and negative level. A pulse generator is used to set the timing.

There is some differences in the positive and negative slew rates. This is because the current mirrors are not perfect.

In the second circuit the positive slew rate is 0.5000 v/us and the negative slew rate is 0.5086 v/us (1.7% difference)



There is minimal overshoot.

I have attached the LTspice models

Regards,

Jay_Diddy_B
* circuit 2.asc (7.89 kB - downloaded 33 times.)
* circuit 1.asc (4.22 kB - downloaded 42 times.)
« Last Edit: March 01, 2025, 04:00:59 pm by Jay_Diddy_B »
 
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Offline pardo-bsso

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Re: Controlled symetric slew rate limiter
« Reply #7 on: March 02, 2025, 12:07:10 am »
Apologies if the question seems basic but what is the purpose/advantage of using a mosfet instead of another bipolar transistor for the reference current?

Thanks.
 

Offline Smokey

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Re: Controlled symetric slew rate limiter
« Reply #8 on: March 02, 2025, 12:52:20 am »
Does it have to be analog?  How about a high resolution DAC just creating the desired waveform?  Maybe add some extra output filtering.
 

Online PCB.Wiz

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Re: Controlled symetric slew rate limiter
« Reply #9 on: March 02, 2025, 02:02:08 am »
Apologies if the question seems basic but what is the purpose/advantage of using a mosfet instead of another bipolar transistor for the reference current?

You mean M1 ?
Couple of advantages :
  • The base current does not create an error
  • Mosfets have a higher output impedance so better PSRR or less current change with voltage
The opamp compensates for the poorer vgs precision.

You can get matched transistors, so they are used in the mirrors, if you could get precision matched vgs mosfets they could be used there too.
 
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Offline Jay_Diddy_B

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Re: Controlled symetric slew rate limiter
« Reply #10 on: March 02, 2025, 02:04:10 am »
Apologies if the question seems basic but what is the purpose/advantage of using a mosfet instead of another bipolar transistor for the reference current?

Thanks.

That circuit has the feedback on the source current. The source current is equal to the drain current, the gate current is zero. If a BJT was used the emitter current would be regulated. The collector current would be the emitter current -minus the base current. This would introduce a small error.

Regards,

Jay_Diddy_B
 
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Offline pardo-bsso

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Re: Controlled symetric slew rate limiter
« Reply #11 on: March 02, 2025, 03:54:00 pm »
Apologies if the question seems basic but what is the purpose/advantage of using a mosfet instead of another bipolar transistor for the reference current?

Thanks.

That circuit has the feedback on the source current. The source current is equal to the drain current, the gate current is zero. If a BJT was used the emitter current would be regulated. The collector current would be the emitter current -minus the base current. This would introduce a small error.

Regards,

Jay_Diddy_B


Thanks Jay and PCB.Wiz, I completely missed that part.
I'm getting rusty.
 


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