Heavy interconnect board layout

[Phaedrus]

I'm pretty much done designing this board, just wanted to put it out there and see if there's anything I might have missed, anything I can tweak or optimize, etc.

Basically the board is an interconnect for a PSU semi-automated test system. It's the part where the PSU outputs, DC loads, datalogger, and oscilloscope probes all come together. I've also put together a voltage "sanity check" to visually indicate if PSU voltage is within a baseline +/-5% tolerance. If it is, the LEDs shine green. If it's out of that spec, the LEDs flash red. Pretty simple. Oh, and it's 300mm x 205mm.

The board has to handle a lot of current, and I wanted it to be physically robust as well, as it's the point where the user comes into contact with the system. So it's built on 0.093" FR-4 with 2oz copper. This increases ampacity of the main current traces, but imposes limits on the voltage check section. You can't have spacing less than 0.011" between traces or pins, or most board makers can't make it without accidental shorts. Also the board has a lot of thermal mass, so I use thermal connections to the ground plane for most smaller components, rather than directly flooding it.

Anyway, was just hoping for some constructive feedback. Thanks!

PS: I chose discrete components over an MCU because this needs to be brain-dead simple and reliable... No random software issues to debug, etc. Plus, it's an excuse to use an NE555 and 74HC logic in a real, useful application, how can you say no to that?

EDIT: I forgot to go back and change it in the schematic, but I decided C7 wasn't useful and decided instead to add a 100nF 1500mA ferrite bead instead.

[Phaedrus]

Shameless bump.

[free_electron]

three transistors to turn on an led ? really ?

now the obvious points are : since this is poer test : kelvin connections ? are you measureing where you need to measure ... i wouldnt use a plane for the return current in this case as you don;t know how it will flow.