DDR3 diff clk termination

[halexa]

Hi,


Struggling to understand how to terminated a differntial clk pair for DRR3 with 100Ohm impedance.

Im using a iMX6 Dual Lite with two DDR3L memory chips with fly-by topology and I cant find a good source how to terminate the clk diff pair.

NXP in their reference design use T-topology and terminates the diff clock with 200Ohm between the pair.

I seen design guides using two resistors with with a cap to DDR 1.35V source voltage. Here I have seen the multiple solutions using 2x100 Ohm and 2x50 Ohm

And guides using serie restors only.

For Fly-by topology what is the best way to terminate the diff clk? 

[darrell]

A single 100 ohm across the pair is simplest and should be sufficient.

50 ohms to VTT (or a cap to GND if you don't have VTT) from each side of the pair gives a common mode impedance of 25 ohms rather than the open of the above. That may help EMI and signal integrity.

200 ohms to GND and 200 ohms to VDD from each side of the pair gives the same common mode Z, but at a higher power consumption.

I've done no termination whatsoever on a Zynq DDR3L clock with a single chip and short traces. Looks good on the scope. Was trying to minimize power consumption there.

[halexa]

Attached picture is what a meant by to resistors and a cap to DRR source voltage.

[asmi]

It's best to run IBIS simulation of your traces if you want to be certain that design will work - you can find IBIS models for both CPU and memory modules on manufacturers' websites. Alternative approach is to just take reference design, but in this case you'd better replicate their layout as precisely as you can as little things matter (like relative positions of components, traces layout, stackup, etc.).

I've just looked at the schematic and PCB layout of Dual Lite SABRE board, and there they use 200 Ohm termination resistors placed just behind last memory IC in a chain. Honestly this is the first time I see such approach, but since the board works, I guess it's good in that case.

What I would've done in this situation is reproduce their reference design and then do some IBIS sims of resulting layout to see if it would work, and what kind of margin it would have.

[asmi]

Attached picture is what a meant by to resistors and a cap to DRR source voltage.

Did you use such approach anywhere? Everywhere I looked it's always recommended to terminate to VTT (which is half of Vddr3 and tracking it).

[simmconn]

Attached picture is what a meant by to resistors and a cap to DRR source voltage.

This is fine. You can also connect the cap to GND instead of VCC.
 

[halexa]

Attached picture is what a meant by to resistors and a cap to DRR source voltage.

This is fine. You can also connect the cap to GND instead of VCC.

As I understand it VTT is only for single ended termination, like Addres and data lines.

Based on the feedback I think i go with my sketch since it makes the most configurable option.There i have the option to not mount the cap if it causes a problem.