DDS Function Gen Layout Review

[PCB.Wiz]

Would I expect inductors of this size to be much larger than 0603, or even 0805? Skimming through mouser, many of the inductors are 1608 or bigger.... just sanity checking.

Digikey shows coilcraft 0402DF series, with high SRF, and 5% tolerances.
 

[jgrossman]

Would I expect inductors of this size to be much larger than 0603, or even 0805? Skimming through mouser, many of the inductors are 1608 or bigger.... just sanity checking.

Digikey shows coilcraft 0402DF series, with high SRF, and 5% tolerances.

Yep, thanks!

[jgrossman]

If wanted a 2nd switched attenuator (e.g. 1/10 ... 1/100)  could be at the output. This would want a mechanical 2 pole 2 trough relay (or manual switch) and choose on both sides of the 50 ohm series resistor or a 3 resistor (I would prefer T form) divider.

I'm having trouble visualizing this. This is the only thing i can conceptualize, but its SPDT not DPDT as you have mentioned, and I'm not really sure of the resistor configuration.

[Kleinstein]

For a +-5 V supply the LMH6639 or AD8055 are candidates for the amplifier.

The filter could still use lower resistors, like 220 ohm, so that the loading from the amplifier is not that significant. It may need a simulation to check the effect of the loading by the amplfier. So R9 and R10 would ideally be a bit larger as R1 and R3 are also loading the filter output. With the amplfier feedback the loading through R1 should be stronger. So R9 and R10 would no longer be the same. Especially R9 may need to be a little larger, as R1 with additional voltage gain is effectively in parallel.

For a 75 MHz DDS clock the low pass filter cross over frequency should be less than 37 MHz, more like 30 MHz so that everything beyound 37 MHz is already well attenuated. The maximum usable frequency for a sine would be some 20-25 MHz. The usable frequency for the triangle is considerably lower anyway - maybe 1 MHz or so.

Inductors are available also in the small form factor, especially the relatively low values or around 1 µH and less. Some ferrite ones may be tricky with the Q droping at the relevant frequencies. However I am not an RF expert.  With a lower impedance and thus smaller inductor values this becomes less of an issue. There is a reason that RF circuits are usually relatively low impedance of some 20-100 ohm as this is the typical cable / trace impedance and parasitics get less relevant. 400 Ohm is already higher than the 379 ohm of free space.

Due to the parasitic capacitance and self resonance of the inductors the capacitors parallel to the inductors should be a little (e.g. 0.1-1 pF range) smaller than calculated in the simulation.

The attenuator switching would need the relay choosing between a path of just the 50 ohm series resistor and a path with a divided down signal. The divider would no longer have the 50 ohm in series, but the ouput impedance of the divider should be 50 ohm. So may be a divider with 56 ohm and 470 ohm.  At the not yet that high frequencies the OP-amp should be OK with the slightly variable load. A true RF style circuit would use a double pole relay and also switch the connection of the divider / 50 ohm and than have a 3 resistor 50 ohm attenuator (e.g. 3 x 33 ohm as a T for a -6db attenuation).

[PCB.Wiz]

Would I expect inductors of this size to be much larger than 0603, or even 0805? Skimming through mouser, many of the inductors are 1608 or bigger.... just sanity checking.

Digikey shows coilcraft 0402DF series, with high SRF, and 5% tolerances.

Yep, thanks!

There are also choices at lcsc, pick a high SRF.

Unless you have very specific RF uses for this,  the output opamp is going to have filtering anyway, and a higher DDS clock will do more than a complex LC filter.

Did you also look at aliexpress DDS modules ? - some of those cost less than the DDS chips, and a board could allow for choices via DIP headers ? 

https://www.aliexpress.com/item/1005002594682266.html
https://www.aliexpress.com/item/4001081438278.html
https://www.aliexpress.com/item/1005002962562189.html

[jgrossman]

Appreciate it, that makes sense now with the attenuation.

What about this circuit to separate the DDS and gain load (could be way off base here, but it worked in sim at least). Ignore whats going on at the top for now, and I haven't modified the filter yet.

[jgrossman]

Unless you have very specific RF uses for this,  the output opamp is going to have filtering anyway, and a higher DDS clock will do more than a complex LC filter.

I'm maxing out the DDS clock at 75MHz.

WRT to aliexpress DDS, yeah if I needed a waveform solution on the cheap, those would probably work. The primary goal for me here though is to learn, so the exercise of building the design is more important to me than overall cost or function, as long as it meets some minimum spec/usability.

[MarkF]

You appear to be driven to design a filter at the nyquist frequency.  No doubt, you've been taught that the nyquist frequency is the highest frequency you can generate.  Which is true (HOWEVER...).  As said before, don't design for the absolute max.  Give yourself a little breathing room.  So, let me give you an exercise and then ask a few questions.

Exercise:
  1) Draw one cycle of a sine wave on a piece of paper.
  2) Draw dots on the sine wave until you think by connecting them you get an acceptable sine wave.
  3) Count the number of dots you drew.

Questions:
  1) Divide your 75MHz AD9834 clock by the number of dots.  What frequency did you get?
  2) How many samples are you going to have at the nyquest frequency?
  3) How well are that many samples going to represent a sine wave?
  4) Now, what frequency do you expect to be able to generate?  Maybe, re-visit your filter design?


Not trying to be a smart a$$ here.  If you already know this, I'm sorry.

[jgrossman]

No offense taken. I'm not really trying to drive signals at 30MHz or whatever, I would probably want to cap that at 15, or even 10. The reason I am shooting for such a comparably high filter is to give plenty of breathing room for the higher harmonics of the triangle wave, which will be going through the filter as well, which as far as I understand even at frequencies like 1-2MHz will only get like 7-15 of the harmonics under 30MHz. Anyways all that to say I'm thinking in terms of maximums to get the best result when I pull back for implementation.

[Kleinstein]

The triangle is limited in useful frequency for more than just harmonics. With the harmonics it is not so much about the really high ones, but about getting phase shift for some 5 times the frequency. Most filters (especially the sharp ones) effect the phase already quite a bit below the cross over. A sine wave output usually does not care about the phase response. Ideally the filter for the triangle is made for a more linear phase, which is corresponding to just a delay in time. So a relatively high cross over frequency makes some sense, but one should still stay below the nyqueist limit.
The other point is that a triange with a low number of points per period is that the peak value can vary. This can add some modulation near the peaks.


The system with the extra buffers should work but is quite some extra effort. A simulation should tell how much the amplifier is actuall loading the filter on one could adjust the loading resistor accordingly. The one for the non inv input to the OP-amp is easy to calculate.
When not going super fast the LM7171 could also be OK with a higher resistor (e.g. 1-4 K) in FB. So I would go for adjusted resistors and a little lower fitler impedance instead of extra buffers. With a USB supply and charge pump for the negative side one is anyway a bit limited in the power, espcially for the negative side.

[mawyatt]

Appreciate it, that makes sense now with the attenuation.

What about this circuit to separate the DDS and gain load (could be way off base here, but it worked in sim at least). Ignore whats going on at the top for now, and I haven't modified the filter yet.

(Attachment Link)

You aren't going to get much of a DDS signal output with C37 and C38 at 0.1uF!!!!

Best,

[jgrossman]

Appreciate it, that makes sense now with the attenuation.

What about this circuit to separate the DDS and gain load (could be way off base here, but it worked in sim at least). Ignore whats going on at the top for now, and I haven't modified the filter yet.

(Attachment Link)

You aren't going to get much of a DDS signal output with C37 and C38 at 0.1uF!!!!

Best,

Oh... sure enough.

The amplifiers have a hard time with the unwanted very high frequency part and demodulate part of it. So ideally there should be at least some filtering before the differential amplifier, e.g. at least some capacitance in parallel to the 220 ohm resistors to ground, maybe also 1 LC filter stage. Filtering before the amplifier is more effort because it is for both signals and should be symmetric.

I think I was trying to follow this advice, but I'm not sure if it's really necessary to have capacitors in parallel with the first load resistor since it also goes through a low pass immediately after...

[Kleinstein]

No extra fitlers in parallel to the initial resistors to set the input side termination / DAC load. There are already calculated size capacitors as part of the filter. Added capacitance would change the filter. If one is really serious one may even want to reduce that capacitance by the output side capacitance of the DAC, which may be a few pF. Not sure if there are specs on this.

[jgrossman]

This is what I've simmed up:



For channel 2, I wanted to convert the singled ended 0-3.3V output from either the aux function or MSB square wave from AD9834 to a differential 0.6V_p-p that matches the AD9834 sin/tri output. This way the offset and coarse attenuation (via switches, not FS_adjust) can be controlled together. Probably also going to put a switch to skip processing on channel 2 so that the 3.3V level signal can be used as a trigger, etc.

One issue I'm having is that at higher frequencies (5-10Meg), I get about 0.83dB attenuation on the sine channel. While this seems OK, I'm not really sure why and would appreciate some insight here.

Also attached the sim .asc, though I changed the opamps to universal opamp2 for ease of sharing. Behaves approx. the same as spice models for the parts I am trying to use.

[jgrossman]

A true RF style circuit would use a double pole relay and also switch the connection of the divider / 50 ohm and than have a 3 resistor 50 ohm attenuator (e.g. 3 x 33 ohm as a T for a -6db attenuation).

When I sim this, the impedance is ~56 ohm.



When you say "3 resistor 50 ohm attenuator (e.g. 3 x 33 ohm ...)", do you mean "50 ohm" as in "around 50 ohm", or am I misinterpreting here? Don't have an amazing grasp of this, so I'm not trying to correct you, just trying to solidify my understanding.

EDIT: Hmm, when I remove the series resistor R4, the output of this sim does get very close to 50 ohm (undershoots a little).

When I was googling, I saw multiple sources that gave me the impression that the impedance of this tee circuit is what the input sees when connected to a load of that impedance. This was backed up with sims utilizing various values of resistors output from here: https://www.digikey.com/en/resources/conversion-calculators/conversion-calculator-attenuator.

For example, if I wanted a 6.02dB attenuation at 121 impedance, it would spit out R₁=40.3296, R₂=161.35191. Connecting a tee attenuator with those values followed by a series 121R to ground, the output of the sim was bang on 121ohm.

So I guess I have a mental disconnect here.

[Kleinstein]

With the attenuator I was wrong with the resistor values - somehow memory tricked me - sorry for that confusion. I think you found a proper calculator for the attenuators.

The 0.8 dB drop could be just part of the fitler response. The filter is not a perfect brick wall. There are compromises with pass band ripple and steepness. Especially with a DDS one does not need it as there is the additional sin(x)/x drop anyway and one may have to correct that. With the fine adjustable amplitude this can be done in SW.

In the simulation the resistor R10 for the output load should be 100 Ohm, as 50 ohm in series as part of the amplifier and 50 ohm external load. For the simulation it would not change much.

The square wave output part looks overly complicated. It makes little sense to go single ended -> differential and than back again.

[jgrossman]

With the attenuator I was wrong with the resistor values - somehow memory tricked me - sorry for that confusion. I think you found a proper calculator for the attenuators.

No worries! Just wanted to make sure I understood what the sim output represented.

The square wave output part looks overly complicated. It makes little sense to go single ended -> differential and than back again.

Yeah, I guess so. I was trying to make it easier to control the dc offset the same for both, not really sure why I was fixated on making it like the other channel. This circuit works with 1 less opamp, and the single LM7171 is marginally cheaper than the LM7372, even if the latter is dual-channel.



It does shift the phase of the input 180deg, though I think that cancels out with the fact the output of the OP U1 on the sine channel is already 180deg out of phase with the output from IOUT, which I think is what maps to the NCO of AD9834 (as opposed to IOUTB which is the complement, I think). Since any other signal passing through channel 2 originates from software, it can just be complemented in sw with no problem.

With the fine adjustable amplitude this can be done in SW.

I would assume this means I have to increase on the gain for channel 1 slightly, since the fine adjust with the FS_adjust pin is purely subtractive.

[MarkF]

I fail to see all this effort to incorporate a DC Offset adjustment for the square/aux channel when there is no amplitude adjustment.  All of the sources will be fixed logic levels.  The 'sign-bit' output of the AD9834 does not vary with FS_adjust.  Most likely you will want this output to be solely positive to some logic device or gate.  In my experience with it, I have found uses for an amplitude adjustment that was 0V to some +V value though (When using a PWM output for example.).

I don't think I would be too worried about filter losses and DC offset errors at this point.  More concerning would be the flatness of the filter in the pass-band.  I had to fine tune (in software) both the gain and the DC offset after the hardware was built.  I suspect you will need small scaling factors in your software too in order to get exact results.  In addition, you will probably have two different scaling factors dependent on whether you have the attenuator switched in or out.

Also, you're forgetting the elephant in the room.  Heat dissipation for the LM7171.

[jgrossman]

I fail to see all this effort to incorporate a DC Offset adjustment for the square/aux channel when there is no amplitude adjustment.  All of the sources will be fixed logic levels.  The 'sign-bit' output of the AD9834 does not vary with FS_adjust.  Most likely you will want this output to be solely positive to some logic device or gate.  In my experience with it, I have found uses for an amplitude adjustment that was 0V to some +V value though (When using a PWM output for example.).

I guess I'm trying to be able to generate 0-centered square waves, but I'm really racking my brain for a reason to have anything other than 0-centered or 0-V₊ on the square/aux channel... and really coming short on the former too, other than "because I can". How do you implement the amplitude adjustment? The easiest way I can think of on the spot is to power the AD9834 from 5V from USB so that sign-bit out is 0-5V, then can be attenuated down to 3.3V, 1.8V, 1V or whatever with discrete steps.

This would also simplify the circuit overall, only needing the single high-speed opamp for the primary channel, and the one lower speed for DC offset.

I don't think I would be too worried about filter losses and DC offset errors at this point.  More concerning would be the flatness of the filter in the pass-band.  I had to fine tune (in software) both the gain and the DC offset after the hardware was built.  I suspect you will need small scaling factors in your software too in order to get exact results.  In addition, you will probably have two different scaling factors dependent on whether you have the attenuator switched in or out.

Yes, this is one of the reasons I want some kind of loopback to the MCU from multiple points to be able to do some calibration and store that information to the internal EEPROM on the STM32. Then some algorithm on the software side to do be able to automate that process when required. I was thinking tapping off a few points:

• DC offset. While I can't directly monitor the whole range (my circuit maps [0,3.3] onto [2.5,-2.5]), I want to measure a few points on the positive side and linearly interpolate that through the range
• Sine output (post diff-opamp). Setting the AD9834 reset bit I should get a mid-scale output, which after performing (1), would allow me to be able to calibrate FS_adjust by adding a DC offset to place the mid-scale output within the middle of the STM32 ADC range. This would be performed both with and without attenuation.

As far as compensating for the insertion loss of the filter over frequency ranges, the only way I could really see that being done automagically is with a fastish ADC (>=100MS/s for a 10Meg signal). That hardly seems worth it here, I'd probably just do this manually.

[MarkF]

• I have no adjustment of amplitude nor DC offset of my digital channel.  I directly routed the sign-bit pin of the AD9834 and a PWM pin of the MCU directly to a BNC connector.  Regrettably, I didn't even buffer the output.  As shown, I suggest using the hex inverter configured for a 50Ω output. 
  
  My MCU and AD9834 are running with a 5V power supply.  I'm old enough to still think in 5V logic.  A hard habit to break.
  
  I don't know how you would do the attenuation for different logic levels.  I would be worried that the switching would destroy the rise/fall times.
  
  
• I fine tuned my scaling factors manually via trial-and-error.  Don't see any reason for anything complex since you will probably only ever need to do this once.  You just need to make sure the gain through the system ends up a little over the max output you want.  That way you can knock a little off the FS_adjust scaling to tune the amplitude.  The fine tuning of the DC offset will mostly be dependent on the resolution of your DAC output and the gain in the op-amp creating the offset voltage to set a precise zero.
  
  
• You may have more variation across the pass-band of your filter than in the rest of the system.  Which you can only minimize in the design phase.  You're not going to have a lot of control afterwards.  The AD9834 is pretty much a setup and let it do it's thing.  You don't really have any low-level control over details.  Trying to determine what it's doing at any precise moment is impossible.
  
  
• Adding a bunch of extra hardware to perform automatic tuning will add to the cost and will need calibration too.  Added switching for it will also be an added risk of failure.  This may be more trouble than benefit.  Also remember, tapping a signal will also change that signal.
  
  Being able to quickly and easily change scaling factors in software would be more of a benefit.  Being able to make a measurement and then enter a correction through a GUI would be less trouble than the extra loopback hardware.
  
  
• Are you sure you're not over-thinking the calibration?  What accuracy are your requirements?  Most likely you're going to dial-in a waveform / measure it on a scope / fine tune it.  You will have to put in much more work if you want a precision instrument here.  I'm guessing 1% tolerances at best.
  
  This is just a basic function generator?  Right?

[jgrossman]

If the STM32 was 5V power-capable, I would probably do that too. The only reason I'm using the STM32 at all is to skill up (I'm a software guy, and some upcoming projects at work are using the STM32). It really is fairly overkill for this application, otherwise.

But anyways, I think you are right about over complicating this. Some twiddle factors set over GUI is probably more than good enough.

[jgrossman]

I've attached a schematic incorporating the feedback I've received so far. A few specific points I want to address:

• For channel 2, because I'm using the hex inverter to buffer the output, I don't have to care about the impedance of the attenuators, right? So I can use simple voltage dividers through relays, like what is shown? Just realized the inverters can't possibly come after the attenuation; not quite sure what I'd like to to do here but it is late so I'll figure it out later. Is there a reason I couldn't omit the parallel 200Ohm resistors and just switch between some attenuating circuits with 50Ohm impedance?
• When I look at BNC connectors, they are labeled 50Ohm. From googling that would be the "characteristic impedance"? I.E., I should not consider them as 50Ohms in series? Sanity check here.
• Is there a more standard way to represent the SPDT symbol for the attenuation in a way that makes sense topologically? The one I grotesquely morphed into the symbol for K3 doesn't look too slick, but the normal one puts the input and output (in this case) on the same side so it can't flow nice and tidy left to right. Curious what others have seen.

[Kleinstein]

The Inverter as digital gates want a full range signal and thus no attenuator infront. The usual logic chips are not strong enough to drive a 50/100 ohm load. The logic gates are also cheap and inverters come as a 6 pack, so why not share the load.

For a variable amplitude one could replace the inverters with AND or NOR gates and than use 4 x 200 ohm resistors as a simple 2 bit DAC by choosing how many of the outputs are active and how many are fixed GND. This would allow levels of 5 V , 3.75 V, 2.5 V and 1.25 V. With slightly different resistors (e.g. a mix with 220 and 180/150 ohm) one could get more and different levels. For the actual levels one would also need to include the output resistance of the chips (some 30-50 ohm).

The BNC connectors are made for 50 ohm characteristic impedance. This does not mean there is a 50 ohm resistance inside, but when used with 50 ohm (e.g. standard coax) cables at both sides it would not be a discontinuity. As the connector is short anyway this would be relevant only for much higher frequencies (e.g. 500 MHz range). Here the 50 Ohm BNC mainly acts like a label, telling the user to use 50 ohm cables and not 75 ohm ones (video standard). 

I think the low pass fitler is too high in impedance. This may not work with the normal 3 mA DAC current (too high a voltage for the DAC) and parasitic capacitance gets problematic. There is a reason that the standard with DDS chips is with 200 ohm termination and sometimes lower for the very fast ones.

The output fitler looksOK in principle, but I would have a larger attenuation step, like -20 dB there. The fine adjustment can be done at the DDS ref.. It is more that one may want a larger range. Still this is only a change in the resistors.

[MarkF]

I think the low pass fitler is too high in impedance. This may not work with the normal 3 mA DAC current (too high a voltage for the DAC) and parasitic capacitance gets problematic. There is a reason that the standard with DDS chips is with 200 ohm termination and sometimes lower for the very fast ones.

I thought you said that the input impedance of the filter was (R31 || R26) and (R32 || R34) which is the 200Ω load wanted by the DDS.  I would not have used 470Ω resistors.  The nearest standard values would be 390Ω or 430Ω.  I indicated 430Ω only because I was using that value elsewhere.  Refer to:  https://www.eevblog.com/forum/projects/dds-function-gen-layout-review/msg5133393/#msg5133393

Are you saying  R31 = R26 = R31 = R34 = 390Ω ?

@jgrossman,
Resistors R23 and R24 forming the voltage divider drive FS_adjust seem to be too high to me.  I would try to make them an order of magnitude lower than R25 (6.8KΩ).  You want the current through the divider to dominate over the current going into FS_adjust.  I don't know what the peak voltage is of a STM32 DAC to suggest values.

Refering to the AD9834 Eval Board, they have a 100nF capacitor on the FS_adjust to ground.  Seems like a good idea to reduce noise and provide a stable reference.

[Kleinstein]

The 600 mV compliance voltage for the DAC output are maximum values.  200 ohm is the maximum valid load see for 3 mA of DAC current. I am not so sure how much the LC filter part may add the the impedance at some frequencies. It should not add much at the low frequencies and R32|| R34 should be OK there. So I would consider 390 ohm the absolute upper limit, maybe better go even lower.  For the upper path R29 is also kind of parallel to R26, so R26 should be somewhat larger. However this does not fully work for the DC part as the OP's input is not at GND, but DC wise lifted and the extra DC offset also adds to this.
AC wise R29 sees the near (e.g. 85%) the inverse voltage and is thus eben more relevant. For the filter the AC part is the more relevant one. In the last PDF R29 with 640 ohm would already be more than enough AC loading, about equivalent to some 350 ohm.

To be on the safe side (avoid distortion from exceeding the 600 mV) I would go even lower in the resistors. The nornal value in appl. notes seems to be 200 ohm.
I would consider 220 ohm for R31, R31. R34 and R26 get than larger due to the additional loading. Probably around 270 ohm for R34 and some 400 ohm for R26. The simulation should help to get the right values here.  The loading due to the differential amplfiier is a bit tricky to calculate in the head.



The point with parasitic capacitance is not directly related to the DAC.  RF circuits just don't work well at high impedance and 400 ohm is already higher than the free space impedance. With higher impedance (e.g. > 200 ohm parasitic capacitance can be an issue). With very low impedance ( < 20 ohm) parasitic inductance is more relevant.