Hey, I am new here. I have asked for reviews on Reddit in the past, but I was told this is a good place for more advanced stuff. I was inspired by a Jay Carlson blog post to make a 50x50mm single-board computer based on the NXP iMX6, for which I got free samples. I'm using JLC's impedance controlled 4 layers stackup: signal, power/GND, power/GND, signal. I decided on the small dimensions and not using 6 layers for the challenge and to save on costs. The PCB was designed in KiCAD 6, all the files are available below for review. Total board cost is around 25 CAD$.
The board is powered through a dedicated USB-C connector. An input load switch is used to limit inrush current, current limiting, reverse protection, etc. A 3-channel buck converter (RT7273) creates the 3.3V, 1.8V, and 1.375V power rails from VBUS. There's current sensing on each rail using an amplifier and the MX6 ADC.
The processor (MCIMX6Y7DVM09AB) runs at 900 MHz, which requires a 1.375V core voltage. Power sequencing for the different rails is done with the buck converter. The power good flag (active high) controls the reset pin (active low). I've used about 30% less decoupling than recommended by the manufacturer due to space constraints.
The processor is connected to a single 512MB DDR3L x16 device (Samsung K4B4G1646E). A lot of swapping was involved during routing: byte groups are swapped and nearly all data lines within a byte were swapped. No attempt has been made to length match any traces since they are very short (all under 30mm) and the device operates at only 400MHz while being rated for 933MHz. Also the trace impedance is closer to 70Ω than 50Ω but I needed thin traces for space so I chose to ignore it. The DDR is powered by the 1.375V rail.
The board also includes a 8GB eMMC 5.1 device. There's no special reason why I decided to include it other than to have the chance to try it. I'm a bit worried about the fine BGA pitch (0.5mm), but worse case scenario I'll just remove it and rely on the micro SD card slot. I've had to use NC pins for routing, and while the datasheet doesn't say anything about it, several sources indicate that it should be fine. The eMMC runs on 1.8V IO and 3.3V core voltages.
There's an Ethernet port with a 100Mbps PHY (LAN8720A, RMII) and a RJ45 magjack. This is the only place where I've used series termination resistors though I'm not sure they are necessary. The PHY runs on 3.3V IO and core voltages.
Finally there's 2 USB 2.0 device ports (USB-C). The ADC is connected to the CC pins of the input power receptable to know the current capability of the power supply, in order to limit current to USB devices to 50 mA if that capability is below 1.5A (hence the load switch per USB port).
I've picked unused processor pins for the GPIO header as to maximize the number of usable peripherals (UART, SPI, I2C, PWM, ADC). I've also used analog switches for current sensing to leave more ADC inputs to the header. All connectors except the GPIO header have TVS protection on them.
A power tree is available on the main schematic, which indicates a maximum input current of 2A. This is probably much higher than actually achievable since the processor, DRAM, eMMC, SD card, Ethernet and USB devices can't all be at maximum capacity all at once. I expect the maximum current to be at most 1.5A.
I appreciate any input on the design!
Files: