A register is usually some form of D type flipflop per bit, so yea, a modest amount of logic.
Note that in most HDLs, a latch is level triggered and a register is edge triggered (And latches are usually a really bad idea, but can be inferred if you are not careful).
Take a look at something like a 74HC74, a jellybean D type flipflop (Which is annoyingly referred to as a latch outside the HDL world), the datasheet lists three critical parameters, a propagation delay, a setup time and a hold time.
The output takes the value the input had at the rising edge of the clock after the propagation delay thru the device, and for that to reliably be the case the input must be stable for the duration defined as the setup time before the clock edge and for the hold time after it (Fail to meet setup and hold and really weird things can happen, the term is metastability and it can be a major pain when you have more then one clock in play).
The key is that conceptually the output of a register takes the state of the input measured at the clock edge, and holds it constant the rest of the time, and that the state of the output updates shortly after the clock edge that sampled the input.
The edge triggering of the update means that the output of the register changes at most once per clock cycle (We will gloss over async set and clear).
Regards, Dan.