Three JFETs? Rather old fashioned.
Tim
An interesting article on F/V from Pease, might be of interest.
http://www.electronicdesign.com/digital-ics/whats-all-frequency-voltage-converter-stuff-anyhow
Also his note on capacitors -
https://www.edn.com/electronics-blogs/anablog/4310008/Bob-Pease-on-capacitor-leakage
http://www.electronicdesign.com/analog/whats-all-capacitor-leakage-stuff-anyhow
Regards, Dana.
Hardly discrete. I was thinking of lots of BJTs and FETs.
How about using the 74HC123? All that's needed is the pulse setting to the correct length, then you have PWM on the output, proportional to the input frequency, which can be filtered to provide a DC voltage.
Regarding the schematic from #1 post: I don't think the input series resistor followed by a shunt zener is helping the linearity here very much.
In that respect that if the zener voltage becomes even slightly close to the control voltage, the current flowing through the input resistor will give you an error.
I'd suggest using a matched pair of diodes (BAV99 for example) as a protection for precision analog instrumentation.
Ok, my bad then. I thought the input is analog input. I would still question the use of D1 though! Is it in line with the comparator's bias current direction? If not, the diode is wrong and should not be there. (shouldn't be there anyway, as the zener already acts as a negative voltage protection!)
I think you'll find those are nMOSFETs - as drawn in the diagram, the gate is spaced from the channel (and the current "arrow" is on the source, no directional arrow at the gate as a JFET would have). But yeah, drawing the bulk portion is a hassle, so I use the bulkless symbol. Sorry for the confusion.
I think you'll find those are nMOSFETs - as drawn in the diagram, the gate is spaced from the channel (and the current "arrow" is on the source, no directional arrow at the gate as a JFET would have). But yeah, drawing the bulk portion is a hassle, so I use the bulkless symbol. Sorry for the confusion.
Oh, you used the bad symbol. No wonder it looked wrong at a glance.
Tim
If the D1 blocks the bias current of the comparator (which in this case does, as the 393 has a PNP input stage), it will certainly act weird. D1 wrong and should not be there. Or just fix it adding a 100k res. down to ground right from the noninverting input of the comparator.
Remeber that opamps (and comparators too!) should always have a dc path to establish a correct biasing. The diode there is same as connecting a cap directly to opamps input. That won't work as expected either.
The diode also makes the comparator unable to work with small voltages.
I think the zener does protect well enough. The comaparator input already provides a diode junction against ground, while the input resistor providing current limiting when negative voltage applied.
Edited with new linearity test of the circuit, as well as a computer drawing of the circuit instead of my pen-paper abomination: see below
So, I recently designed a prototype board - which is an entirely different story; basically I was tired of prototype boards being either very expensive ($10+ a pop) or very, very poor. So I got the first delivery - the family of THT boards - and thought it would be cool to make some demo circuits with them.
The first circuit is a frequency/voltage converter, which outputs a voltage proportional to the input frequency (1V/10KHz, but is settable). Basically, the input is converted to a square wave, then differentiated through a very-high frequency high pass filter. The positive-going pulses (i.e. the square wave sloping upwards) is then accumulated into a capacitor, which is buffered and output to a separate holding stage, and finally conveyed to the output stage. Therefore, the concept is a transfer of charges. The two first capacitor sections have clocked emptying-to-ground through nMOSFETs, and the last section (the "hold" capacitor) gets set in a very short burst of transfer from the 2nd cap (<10µs), by again high-pass filtering its clock to ensure a very short pulse duration.
Finally, the content of the hold capacitors (two Mylar caps in parallel) is amplified to provide the desired output level. A practical measure is 1V/10KHz, but can also be set at 10mV/KHz or similar.
The circuit - See full resolution
Obviously, you should consider the voltage rails - the LMC6482, which is the buffer/amplifier dual opamp due to its RRI/O capabilities and low offset voltage, can only handle a relatively limited supply voltage range.
Anyway - I've tested it from 10Hz to 120KHz, and it has remained fully linear over this entire span! So, as far as I am concerned, this is a success - linearity over more than 4 decades/orders of magnitude!
And for those board fanatics - the actual prototype board,
The board - See full resolution
EDIT: Linearity measurement, 0 to 200 KHz - including the optional RC filter from the schematic with R=5K6, C=4.7µF
Input is taken from a BNC plug - output on a pair of leads (single-ended output plus Gnd). Apart from the actual F/V converter, the board also has a discrete LDO regulator (for the 3.3V rail) not included in the schematic. This uses a TS27L2 op amp and a TIP32 high-gain PNP power transistor.
Anyway - feedback is more than welcome, both on this circuit and the actual prototype board. The prototype board has two sections that are similar to solderless breadboards - that's why the DIP chip section of the board is quite neat compared to the freeform stuff underneath. Additionally, there are three global buses (two interleaved on the sides, and one in the middle), that helps reduce clutter somewhat. In this case, the outer two buses are CLK and -CLK and the central bus is just GND for convenience.