DIY Current load - PMOS design do not work

[Halide]

Hello everyone,

I am trying to build a current load based on a PMOS transistor. I need it to simulate a load for another project, where I want to test the hardware, especially the low-side switches, and verify how the PCB handles higher currents. This is the reason why I decided to build the load using a PMOS transistor.
I designed a simple circuit, as shown in the attached schematic, and simulated it. In simulation, it works quite well.
However, after assembling and soldering the circuit, I cannot find a stable operating point. I have tried different values for R72, C36, and C33, but I have not been able to find a combination that allows the circuit to operate smoothly.
I still see oscillations, as shown in the attached oscilloscope capture. The waveform was measured at the gate of the IXTH90P10P transistor.

Could you please help me debug this design? I am running out of ideas about what might be causing the instability or what could be wrong with the circuit.

Thank you in advance for your help!

[pqass]

Do you have long leads to the DUT?
Maybe the feedback loop is too long with the chosen components (leading to about 1Khz oscillation); shunt to diff amp to error amp to NPN to PFET.

There is a simpler way to shorten the feedback loop. See attached with simulation here (adjust setpoint with slider on right margin).
The attached is for a HV CC source but if you don't need to exceed the op amp voltage supply, then you can remove the zeners.

EDIT: now updated the PFET model for IRFP250 and changed setpoint to 0..1V=0..10A
EDIT2: duh, wrong FET, should be IRF9520

[David Hess]

U11 is not doing anything to help performance and is reducing phase margin, so design the circuit without it.  Any level shifting can be moved to the input of U12.

Common emitter Q3 within the feedback loop adds variable voltage gain depending on operating point, making frequency compensation more difficult.  Either degenerate it to make transconductance and thereby voltage gain constant, or remove it.

[mtwieg]

Not surprising that you see stability issues.

U11 is not doing anything to help performance and is reducing phase margin, so design the circuit without it.  Any level shifting can be moved to the input of U12.

If the current sensing is on the high side but the control voltage is ground referenced, I'm not sure there's a way to do everything with a single opamp.

But at the very least Q3 should eliminated. Can just drive the gate of Q4 with U12 (assuming U12 output can extend up to the supply rail) and invert the gain of the U12 or U11 stage.

Also remove C33. It's slowing down the feedback and ruining the CMRR of the differential amp.

[Halide]

Hi!

Do you have long leads to the DUT?

Around 1m, but feedback loop is on the PCB with traces as short as possible. I've build NMOS version of that circuit and it work in the same environment. So i do not think that cable lenght change something.
Additionally on your schematic, how current feedback loop work, I can't understood it?

U11 is not doing anything to help performance and is reducing phase margin, so design the circuit without it.  Any level shifting can be moved to the input of U12.

I need differential amplifier for high side current measuring so I need two op-amps I think - one for current measurement and second as compactor.

But at the very least Q3 should eliminated. Can just drive the gate of Q4 with U12 (assuming U12 output can extend up to the supply rail) and invert the gain of the U12 or U11 stage.

Also remove C33. It's slowing down the feedback and ruining the CMRR of the differential amp.

I will try to remove C33 and share result (I can't check it today unfortunately).
Before I add the Q3 I have design with direct Q4 drive but have stability issue too.
I've connected the current measurement circuit to the noninverting input and setpoint to inverting input
I have only photo of oscilloscope with noises so quality is not perfect, but here I can't found the stable point too (on oscilograms the baste what I can do)

[hickorystick]

Try increasing C36 to 1uF, or larger.

(per your first schematic)

[PCB.Wiz]

C32 is also counter productive.
If you can’t get the dual amp stable, an alternative approach is to use a single amp as the classic P-MOSFET current regulator hi side, and use a small nmos+op amp to level shift your reference to the hi side.
how fast do you need this?
Note 10 amps at 12 v into milliohms, is impractical power demand from a single mosfet.

[pqass]

Do you have long leads to the DUT?

Around 1m, but feedback loop is on the PCB with traces as short as possible. I've build NMOS version of that circuit and it work in the same environment. So i do not think that cable lenght change something.
Additionally on your schematic, how current feedback loop work, I can't understood it?

I had an issue with oscillations too in my first load that was eliminated when the lead length to the DUT was shortened.  It could also be the gauge of the wire used; possibly due to extra inductance.

Attached is a simplified, low voltage version (simulation here).
The first resistor divider gives Vcc/2 at the op amp +in.   The second resistor divider can only give Vcc/2 at the op amp -in if both the Vshunt == Vsetpoint.
As the current ramps up, the -in > +in which drives the op amp output toward GND, which turns on the PFET hard.  Until it overshoots (Vshunt > Vsetpoint momentarily; also -in < +in), then the op amp output pulls up toward Vcc (turning off the PFET), until an equilibrium is reached.

I had to raise the Vcc to +15V because @10A, Vshunt = 1V and the op amp model is a 741 which can only output to 1.5V above GND.  An LM358 (or just about any other modern op amp) would work better as it can get down to GND.

Also, the IRF9520 is a poor choice as it can't do 10A by itself.  But you could parallel the circuit (using two 0.2R shunts) fed from the same Vsetpoint input.  Or find a better PFET.

[Halide]

Try increasing C36 to 1uF, or larger.

(per your first schematic)

Ok, will check that. For that test, should I remove the C33 too?

C32 is also counter productive.

I put it to provide smooth setpoint but your suggestion is to remove it? Do that cap can affect circuit stability?

If you can’t get the dual amp stable, an alternative approach is to use a single amp as the classic P-MOSFET current regulator hi side, and use a small nmos+op amp to level shift your reference to the hi side.
how fast do you need this?
Note 10 amps at 12 v into milliohms, is impractical power demand from a single mosfet.

For final solution I want to use two mosftes with active cooling.
That circuit do not need be fast. General I just want to set one setpoint per test, so when I need to change the setpoint I will disable the load.

I had an issue with oscillations too in my first load that was eliminated when the lead length to the DUT was shortened.  It could also be the gauge of the wire used; possibly due to extra inductance.

The first resistor divider gives Vcc/2 at the op amp +in.   The second resistor divider can only give Vcc/2 at the op amp -in if both the Vshunt == Vsetpoint.
As the current ramps up, the -in > +in which drives the op amp output toward GND, which turns on the PFET hard.  Until it overshoots (Vshunt > Vsetpoint momentarily; also -in < +in), then the op amp output pulls up toward Vcc (turning off the PFET), until an equilibrium is reached.

I had to raise the Vcc to +15V because @10A, Vshunt = 1V and the op amp model is a 741 which can only output to 1.5V above GND.  An LM358 (or just about any other modern op amp) would work better as it can get down to GND.

Also, the IRF9520 is a poor choice as it can't do 10A by itself.  But you could parallel the circuit (using two 0.2R shunts) fed from the same Vsetpoint input.  Or find a better PFET.

Oh, ok now I can see how that circuit should work. I will try to use it if my solution do not startup - I want to put some effort for my design to find bugs (with EEVBLOG forum help  ) and understood why it do not work now.

But still I can't see reason why cable length can affect that type of load. This is fully linear device and I do not changing setpoint during operation. The load type is resistance so it make no sense for me

[MarkF]

You removed the NPN transistor, but you still need the series resistor to the MOSFET gate.
Start with 100 Ω.  The resistor is there to handle the MOSFET gate capacitance.

And you also need the 2nd opamp because the sense resistor is so small that you need some gain.
I'm just not sure that it's connected properly for high side sensing.

I see you're flipping the (+) and (-) opamp inputs.  Both opamps need to be examined regarding
which is correct.

It is so difficult to analyze your schematic since it is drawn upside down.
Put the power on the top and ground at the bottom as expected. 
Flipping the P-channel MOSFET upside down.

[David Hess]

U11 is not doing anything to help performance and is reducing phase margin, so design the circuit without it.  Any level shifting can be moved to the input of U12.

If the current sensing is on the high side but the control voltage is ground referenced, I'm not sure there's a way to do everything with a single opamp.

I need differential amplifier for high side current measuring so I need two op-amps I think - one for current measurement and second as compactor.

Move the error amplifier to the high side, and use the difference amplifier to move the low side control signal to the high side to drive the error amplifier.  This assumes that your operational amplifiers have a common mode input range which includes the high side.  Some do.

[MariuszD]

It is important that the tested circuit draws current without interruptions. If the current is interrupted, the amplifier will saturate and the Vgs voltage of the PMOSFET will be at its maximum. Reconnecting the load will cause short circuit, and damage to the transistor.

The fewer amplifying elements in the feedback loop, the easier it is to achieve stability. It is not true what MarkF writes:

And you also need the 2nd opamp because the sense resistor is so small that you need some gain.

The signal from the shunt is not small at all. OPA192 has a gain of 120dB. That means 1µV change at the input corresponds to a 1V change at the output. This amplifier will regulate the voltage on the shunt with an accuracy better than 10uV if the PCB layout is good.

The simplest method of frequency compensation is the dominant pole. We limit the bandwidth of only one amplifying stage. Therefore, C32 and C37 need to be removed. To keep C32, it would have to be outside the loop.

[Halide]

It is important that the tested circuit draws current without interruptions. If the current is interrupted, the amplifier will saturate and the Vgs voltage of the PMOSFET will be at its maximum. Reconnecting the load will cause short circuit, and damage to the transistor.

The fewer amplifying elements in the feedback loop, the easier it is to achieve stability. It is not true what MarkF writes:

And you also need the 2nd opamp because the sense resistor is so small that you need some gain.

The signal from the shunt is not small at all. OPA192 has a gain of 120dB. That means 1µV change at the input corresponds to a 1V change at the output. This amplifier will regulate the voltage on the shunt with an accuracy better than 10uV if the PCB layout is good.

The simplest method of frequency compensation is the dominant pole. We limit the bandwidth of only one amplifying stage. Therefore, C32 and C37 need to be removed. To keep C32, it would have to be outside the loop.

Removing C37 and C32 to resolve my issue!
But to be honest I'm not fully understood why removing C32 helps - I mean I supposed it slow down the feedback loop but do my thought are correct?
Additional I add 200 ohms gate resistor.

[MariuszD]

But to be honest I'm not fully understood why removing C32 helps - I mean I supposed it slow down the feedback loop but do my thought are correct?

After the changes with #4, C32 ended up in the feedback loop U14. I don't feel like doing a detailed analysis, but this increases gain in the high-frequency range would be strange if it didn't cause instability.

To check whether the system is truly stable or just on the edge of stability, see how it reacts to a step change in the setpoint. For such a test, there should be nothing in the circuit that would slow down this step change.

[mtwieg]

Move the error amplifier to the high side, and use the difference amplifier to move the low side control signal to the high side to drive the error amplifier.  This assumes that your operational amplifiers have a common mode input range which includes the high side.  Some do.

Not doubting you, but I'm having trouble translating your description to a schematic.

Anyways you're also right about C32 in the second version of the schematic.

But to be honest I'm not fully understood why removing C32 helps - I mean I supposed it slow down the feedback loop but do my thought are correct?

Look carefully at the U14 circuit in the second schematic. You can look at it two ways:
1. Considering the setpoint as the input (and the output of U13 fixed), it's an inverting amplifier. For an inverting amplifier, the inverting input is (ideally) considered a virtual ground, thus putting the capacitor C32 from there to actual ground does nothing to filter the setpoint.
2. Considering the feedback from U13 as the input (and the setpoint fixed), it's a non inverting amplifier. At high frequencies, its gain is determined by R75 and C32, with the impedance of C32 being in the denominator. Thus it will act as a differentiator, with gain increasing with frequency. That's basically guaranteed to make the feedback loop unstable.

Adding a resistor between C32 and the noninverting input of U14 would result in the setpoint being lowpass filtered without making U13 a highpass in the feedback path. Maybe you meant to use R60 for this (R60 has no effect on the circuit as drawn).

[David Hess]

And you also need the 2nd opamp because the sense resistor is so small that you need some gain.

The reason the 2nd operational amplifier does not help performance is that it has the same characteristics as the error amplifier; they are the same types.  The error amplifier can operate with a small signal just as well as the 2nd operational amplifier.

If the 2nd operational amplifier was a different type with greater precision, then things would be different.

Of course it *is* being used to create a level shift for the circuit to operate, but that is just because of the circuit design.  The level shift within the feedback loop is not required if a different circuit topology is used.

[ledtester]

I have a question (and hopefully I'll learn something either way)...

In a low-side electronic loads using a N-channel MOSFET the frequency compensation cap feeds back to the inverting input of the opamp controlling the MOSFET. However, in this implementation the roles of the inverting and non-inverting inputs are reversed due to everything being done on the high side with a P-channel MOSFET. Should C38 (per the schematics in reply #4)  be connected to the non-inverting input of U14?

[MariuszD]

@ledtester If you connect a capacitor to the non-inverting input, there will be positive feedback.

[David Hess]

In a low-side electronic loads using a N-channel MOSFET the frequency compensation cap feeds back to the inverting input of the opamp controlling the MOSFET. However, in this implementation the roles of the inverting and non-inverting inputs are reversed due to everything being done on the high side with a P-channel MOSFET. Should C38 (per the schematics in reply #4)  be connected to the non-inverting input of U14?

It depends on which way difference amplifier U13 is hooked up.  Its inputs are symmetrical, so it can invert the sense of the feedback signal.  In the original schematic, the common emitter bipolar transistor also inverted the function of the error amplifier's inputs.  In practice, there may be reason to apply the global feedback to one input or the other so the designer can choose by swapping the inputs of the difference amplifier.