DIY OISC Computer

[adept]

Haha, I'm sure that most forum people have seen a topic or two like this one before. I know I have! This one isn't like most others though. For starters, I have the design completed. This is mostly about the nuances of laying out the high frequency PCB. So, lemme catch anyone reading this up to speed.

• I have an 8 bit OISC computer designed for scalar parallelization and word-size.
• The computer works on one instruction, which is subtract and branch is less than or equal to zero. (SUBLEQ)
• I have several working programs. One applies a median filter to an 8 color 32x32 image. Another subtracts two numbers gathered from the keyboard, checking to make sure they are numbers. Another that prints "Hello World".

So, on to the issues. I am currently in the process of laying the PCB out in ExpressPCB. (Please don't start a flame war on this. I know how to use other CAD tools, but because I am intending on building this PCB myself, ExpressPCB makes the fastest prototypes for me, over KiCAD. (I dunno about Eagle, I hate it... lol)) I have a 40 MHz oscillator immediately running into a frequency divider that makes 4 nice clean, sequential pulses to run my logic in the order I need to run it. It branches and then runs into the program counter which ends up running into the ROM program, at it's raging 40MHz still. But after it comes out of there, everything is running at 10MHz. What PCB precautions do I have to take with such a fast clock? I'm extremely weary of running that thing anywhere. I think the total length of the antenna so far is about 6 inches max. I'm having trouble printing out the PCB, so I'm really sorry. It is two layers with no ground plane. I'm afraid that the ground plane will make parasitic capacitance and reduce the frequency response of the traces. My engineer father says that isn't the case, but it makes sense to me so I haven't put one in. That's about it.

[Kremmen]

Forget the parasitic capacitance, it won't matter. Instead, understand how every signal needs a path for the return current as well. The return current is equally part of the signal loop. It is just our way of thinking and creating schematics that tends to hide this fact from view. The higher the frequency, the more tightly the return current follows the path of the forward signal current. If you force the return current to follow a different route, the signal will be all over the place with reflections, EMI radiation and other problems. For that reason planes are necessary at high frequencies. In this sense 10 MHz and even 40 MHz is not really a high frequency, but it would be better to observe sound design practice nevertheless. So, again daddy knows best. Just do it.

[adept]

Okay, no problem! Should I also have a plane for the 5 volt supply as well? It would be certainly not reduce the length of the power traces. I of course they don't have any kind of signal on them, so they shouldn't be a problem. And tomorrow is pcb layout day, and so I'll be doing that all day.

[Kremmen]

Well if you keep to a 2 layer board you can't have 2 power layers because then you are left with no signal layers... The obvious solution would be a 4 layer board but i guess here it would be overkill.
What i would do and have often done in fact, in a case like this is to use a 2 layer board with bottom layer dedicated to ground plane as far as possible. The last bit means that i do route some signals there as well, but always keeping the return current paths in mind, so as not to interrupt the plane with a transverse trace across a return path. Not the easiest thing to do in all cases, but usually with time and patience you will get there. Then the top layer is mostly reserved for positivce supply routing and signaling. All unused area on top is flooded with copper connected to supply voltage, thus creating low loss bypass capacitance against the ground plane. Works like a charm, at least if you keep below say 50 MHz, maybe somewhat higher, and give priority to HF signal routing.
This method won't really work anymore if you get to frequencies where signals need to be terminated and length matched. Then you are in transmission line land, and quite different rules apply. Making a transmission line with proper impedance levels in 2 layer is cumbersome and 4, 6 etc layers are indicated for purely electrical reasons. But not at 40 MHz yet, so my recommendation above stands.

[nctnico]

Well if you keep to a 2 layer board you can't have 2 power layers because then you are left with no signal layers... The obvious solution would be a 4 layer board but i guess here it would be overkill.

What I used to do for these kind of board is use a grid for power distribution and a 100nf decoupling capacitor at the crossings. This gives each chip 4 feeding points from a 100nf capacitor.

[Kremmen]

Grid is definitely better than a tree. The latter will only guarantee that maximum pessimality is achieved in the overall current routing. Nothing beats planes but the next best solution is to minimize the loops the current needs to travel to complete the circuit. Basically one should have a hierarchical system of capacitive storage along the supply conductors. For anything considered fast the final caps should be right next to the package pins. These should in turn be supported by caps along the supply route, not just at the PSU circuit itself. But of course you will get away with much less when the signal transitions are slow. And they should be slow unless they need to be fast for a reason.

[adept]

Awesome guys! I didn't quite finish today. It irks me I didn't get it done because now it's on the back burner for the week... I do want to add in that the top layer is only very scarcely populated, so I'm thinking a ground plane will be fine. I'm pretty excited to show off the board soon. Unfortunately my PDF printing isn't working, so I can't tout what I have so far. I'll try and get that going asap. Anyway, it's sleep time for me now in the US. I'll think about it more come morning!