Do you flood your PCBs?

[MikeF]

Something I have wondered for a while - when, if ever, should you flood the top and bottom of your PCBs with copper?

Mike

[Fungus]

If you've got the layers then the answer is "always".

[djQUAN]

I usually do. Makes self etching PCBs faster and saves a lot of etchant too.

[DanielS]

I flood by default, unless I have specific reasons or requirements not to, such as around high voltage traces where clearances would remove most of it anyway.

[T3sl4co1l]

Always, providing you have sufficient clearance for nodes which require it (high voltage, low capacitance).  And stitching between top and bottom!

I don't usually bother on multilayer designs, since there's solid copper inside and figuring out where to put stitching vias gets complicated between four layers.

Tim

[technix]

I do, but usually I don't stitch since I actually run opposite power rails on different layers. This essentially forms a giant board wise decoupling cap with a few tens of pF capacitance which filters out higher frequency noise. Lower frequency noises are dealt with using 100nF/220nF MLCCs scattered around the board next to the chips, and one electrolytic or two at the input.

[Pjotr]

If you have a ground plane on the bottom, you have to balance that copper area on top (and eventually on mid layers). Otherwise your boards will not stay flat due to thermal expansion differences between the copper and body material.

[John_ITIC]

Something I have wondered for a while - when, if ever, should you flood the top and bottom of your PCBs with copper?

Mike

One specific example would be to use the unused areas of the top or bottom layers as power planes. This will allow you to get away with a lower layer count of the PCB. For example, I often work with FPGA designs, where 0.9V, 1.2V, 1.8V, 3.3V is needed on the same PCB. Use dedicated power planes for the lower voltage / higher current power rails. Then use top/bottom fill for the remaining power rails.

Utilizing top and bottom fill can also increase the overall power plane capacitance for a particular power rail.
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an574.pdf

/John.

[Tombs Balsam]

Something I have wondered for a while - when, if ever, should you flood the top and bottom of your PCBs with copper?

Mike

What do you mean by this? flood  = Etching the cooper?
I think it is a good way to choose with a PCB fab, which I thick maybe better than making at home.
I just a got a good recommend of a Chinese fab, you can also have a try www.pcbway.com/e
Hope it can help you

[Phoenix]

I'd say often, but not always. A lot of my designs are for power electronics/switching converters. Copper on top of copper result in capacitive coupling - this needs to be controlled in a high dv/dt circuit.

E.g. a circuit I've been working on lately involves several nodes switching 500V at a rate about 25V/ns. We decided that it would be better to have smaller tracks and wear the increase in impedance (but still try to keep a minimum inductive loop area) to limit capacitively coupled currents to earth/chassis for EMI requirements

[zapta]

Something I have wondered for a while - when, if ever, should you flood the top and bottom of your PCBs with copper?

Mike

What do you mean by this? flood  = Etching the cooper?
I think it is a good way to choose with a PCB fab, which I thick maybe better than making at home.
I just a got a good recommend of a Chinese fab, you can also have a try www.pcbway.com/e
Hope it can help you

Something I have wondered for a while - when, if ever, should you flood the top and bottom of your PCBs with copper?

Mike

What do you mean by this? flood  = Etching the cooper?
I think it is a good way to choose with a PCB fab, which I thick maybe better than making at home.
I just a got a good recommend of a Chinese fab, you can also have a try www.pcbway.com/e
Hope it can help you

Tombs, beware of pcbway. They have terrible reputation and many people avoid them because they spam electronic forums.

[T3sl4co1l]

I'd say often, but not always. A lot of my designs are for power electronics/switching converters. Copper on top of copper result in capacitive coupling - this needs to be controlled in a high dv/dt circuit.

Not enough I'd say to matter -- signal traces yes (500V divides down to a logic level bump, with mere fractional pF, if the node has, say, a passive pull-up), but power circuits, the additional capacitance and reduced inductance is usually beneficial (getting the equivalent loop impedance closer to sqrt(L/C) ~= V+ / Iout).

Interesting to note that, if you need isolated gate drivers at that speed, optos won't cut it.  Most of the magnetic isolator types will do (e.g., ADuM2201 is good for 40V/ns).

E.g. a circuit I've been working on lately involves several nodes switching 500V at a rate about 25V/ns. We decided that it would be better to have smaller tracks and wear the increase in impedance (but still try to keep a minimum inductive loop area) to limit capacitively coupled currents to earth/chassis for EMI requirements

I've done 700V at 40V/ns, and I intentionally added loop inductance and a Vpk snubber to control peak current and commutation losses.  That may be an exceptional case compared to yours, because the transistors were quite large (CJO ~ 5nF).  If this is for just a few amps, the loop time constant pi*sqrt(LC)/2 probably won't be large enough to bother with.

If the loop time constant is less than the gate or drain risetime, the L/C parts will charge/discharge largely during the rise/fall time, burned as switching loss.  Which probably means it's small and easily managed.  If not, you should probably consider snubbing it (with dI/dt (i.e., stray inductance), dV/dt or Vpk types, and controlled impedance).

Tim

[poorchava]

Flooding is almost always a good option unless you have a specific reason not to have copper in particular area, such as HV, noise coupling, EMI, capacitance etc. Flooding ensures, that there is an even amount of copper to be removed between any two given cunductors and this results in a more uniform etching. In DIY setting it also saves etching solution if you care about that.

In more advanced setting, it is for example not advised to leave large unfilled areas on internal layers of a pcb, as this causes uneven pressure during lamination and can result in warping of the PCB.

[tron9000]

Definately. Just keep your isolation between the plane and trace the right distance and should be connected to a reference potential (0V, GND or even PE/chassis GND if designing with mains on the PCB).

http://www.desmith.net/NMdS/Electronics/TraceWidth.html

have not seen copper pour between 2 traces that are at high voltage (mains - 240V AC), on a PCB that had dimension constraints, essentially the isolation gap for each trace meant that there was no room for copper pour. So worth bearing in mind. But on low voltage stuff, its always the best way.

[Phoenix]

I'd say often, but not always. A lot of my designs are for power electronics/switching converters. Copper on top of copper result in capacitive coupling - this needs to be controlled in a high dv/dt circuit.

Not enough I'd say to matter -- signal traces yes (500V divides down to a logic level bump, with mere fractional pF, if the node has, say, a passive pull-up), but power circuits, the additional capacitance and reduced inductance is usually beneficial (getting the equivalent loop impedance closer to sqrt(L/C) ~= V+ / Iout).

Interesting to note that, if you need isolated gate drivers at that speed, optos won't cut it.  Most of the magnetic isolator types will do (e.g., ADuM2201 is good for 40V/ns).

I've done 700V at 40V/ns, and I intentionally added loop inductance and a Vpk snubber to control peak current and commutation losses.  That may be an exceptional case compared to yours, because the transistors were quite large (CJO ~ 5nF).  If this is for just a few amps, the loop time constant pi*sqrt(LC)/2 probably won't be large enough to bother with.

Tim

What sort of topology was this?

It definately does matter when you're trying to meet conducted EMI requirements and your switches and drive circuit are attached to the chassis. The circuit has 3 phase legs, with high side bootstrapped switches. So the isolator, votlage regulator circuit and FET driver circuit are seeing the 25V/ns and are also sitting on the chassis. We're using a Si8233 which uses capactive coupling over the isolation barrier, it's rated at 45kV/us. I am aware of the the ADuM series, but they weren't usable for us.

And your problem was probably a bit different, these switches have little capacitance around 100pF (650V 30A device). In fact we had to externally increase the Cgs to allow a reduction in Rg to prevent the opposite switch turning on during the driven switches transition (due to miller capacitance).

[Tombs Balsam]

NOTE: This message has been deleted by the forum moderator Simon for being against the forum rules and/or at the discretion of the moderator as being in the best interests of the forum community and the nature of the thread.
If you believe this to be in error, please contact the moderator involved.
An optional additional explanation is:

[Niklas]

Tombs Balsam, the way you are writing it, definitely falls within the spam category. Some newspapers in Sweden tried the concept of rewriting an advertisement as an article and also published it without any message like "this article is sponsored by ...". They were not very successful and had to end with their practice soon after being caught and laughed at in social media.

You posting is very similar to an rewritten ad, except for that almost all the info that I usually look for from a PCB manufacturer is missing. I am not going to tell you what is missing so that you can edit the spam. Pretty much everything you have posted so far here in this forum is advertisements.

[Tombs Balsam]

Tombs Balsam, the way you are writing it, definitely falls within the spam category. Some newspapers in Sweden tried the concept of rewriting an advertisement as an article and also published it without any message like "this article is sponsored by ...". They were not very successful and had to end with their practice soon after being caught and laughed at in social media.

You posting is very similar to an rewritten ad, except for that almost all the info that I usually look for from a PCB manufacturer is missing. I am not going to tell you what is missing so that you can edit the spam. Pretty much everything you have posted so far here in this forum is advertisements.

Hi, Niklas. Thanks for your sincere reply to me.

I agree with you. I will notice it in future. Thanks

[T3sl4co1l]

It definately does matter when you're trying to meet conducted EMI requirements and your switches and drive circuit are attached to the chassis. The circuit has 3 phase legs, with high side bootstrapped switches. So the isolator, votlage regulator circuit and FET driver circuit are seeing the 25V/ns and are also sitting on the chassis. We're using a Si8233 which uses capactive coupling over the isolation barrier, it's rated at 45kV/us. I am aware of the the ADuM series, but they weren't usable for us.

Yikes, that much dV/dt for a mere motor driver?!  I hope you're running at high frequency (>200kHz?) and filtering heavily (but hey, filtering means low EMI, so that's good).

Everything going to chassis is a good thing, so long as you can attenuate all the escape paths for noise.  Lots of Y caps and CMCs, that kind of thing.  For both input and output sides.

And your problem was probably a bit different, these switches have little capacitance around 100pF (650V 30A device). In fact we had to externally increase the Cgs to allow a reduction in Rg to prevent the opposite switch turning on during the driven switches transition (due to miller capacitance).

Yes, my case the transistors were big old VDMOS.  But don't have any illusions: yours are likely *just* as bad, at certain conditions.  I'm guessing those are SuperJunction type?  (Even if they don't use that term in the datasheet, you can tell because the Crss, Coss vs. Vds drops precipitously around 20-50V, and remains very low (~pF) or even rises slightly, in the >100V range.)  The difficulty there is, when one side turns on, it has to charge the opposite side capacitance, which looks like reverse recovery because it's such a massive capacitance (~nF) for low voltages.  The charge (Qd) still may not be much, but because it's charged through a huge fraction of Vdd (<50V Vds means the other transistor was dropping, what, 300V+ during that 'recovery' phase?), the switching losses can still be just as large as with VDMOS.

If your load is inductive, and you can afford to wait the dead time for the reactive current to commutate the inverter voltage, you get ZVS with almost zero switching loss.  Unfortunately, few real circuits (like motor controllers and inverters) have such a load characteristic in general, so it's something you can only take advantage of when given the opportunity...

Tim

[Phoenix]

It definately does matter when you're trying to meet conducted EMI requirements and your switches and drive circuit are attached to the chassis. The circuit has 3 phase legs, with high side bootstrapped switches. So the isolator, votlage regulator circuit and FET driver circuit are seeing the 25V/ns and are also sitting on the chassis. We're using a Si8233 which uses capactive coupling over the isolation barrier, it's rated at 45kV/us. I am aware of the the ADuM series, but they weren't usable for us.

Yikes, that much dV/dt for a mere motor driver?!  I hope you're running at high frequency (>200kHz?) and filtering heavily (but hey, filtering means low EMI, so that's good).

Everything going to chassis is a good thing, so long as you can attenuate all the escape paths for noise.  Lots of Y caps and CMCs, that kind of thing.  For both input and output sides.

And your problem was probably a bit different, these switches have little capacitance around 100pF (650V 30A device). In fact we had to externally increase the Cgs to allow a reduction in Rg to prevent the opposite switch turning on during the driven switches transition (due to miller capacitance).

Yes, my case the transistors were big old VDMOS.  But don't have any illusions: yours are likely *just* as bad, at certain conditions.  I'm guessing those are SuperJunction type?  (Even if they don't use that term in the datasheet, you can tell because the Crss, Coss vs. Vds drops precipitously around 20-50V, and remains very low (~pF) or even rises slightly, in the >100V range.)  The difficulty there is, when one side turns on, it has to charge the opposite side capacitance, which looks like reverse recovery because it's such a massive capacitance (~nF) for low voltages.  The charge (Qd) still may not be much, but because it's charged through a huge fraction of Vdd (<50V Vds means the other transistor was dropping, what, 300V+ during that 'recovery' phase?), the switching losses can still be just as large as with VDMOS.

If your load is inductive, and you can afford to wait the dead time for the reactive current to commutate the inverter voltage, you get ZVS with almost zero switching loss.  Unfortunately, few real circuits (like motor controllers and inverters) have such a load characteristic in general, so it's something you can only take advantage of when given the opportunity...

Tim

Who said it was a motor drive, it's just very small. H bridge output, 200kHz carrier frequency (scope to increase it to 400kHz) and a filter design hoping to meet IEC EN 61000-3-2 (gotta build that part still).  Adding more chokes goes against the philosophy of making it smaller, and the total Y capacitors are limited by other leakage requirements. Lots of competing design criteria - good for an engineering workout.

I wish I could discuss curves, but these are pre-production transistors and not yet fully qualified/quantified (GS66508P-E04). We're still learning how they behave as we go. The superjunction MOSFETs appear to be the target competition of the GS66508P (except for the order of magnitude price difference).