Author Topic: Driving the gates of paralled FET's?  (Read 1685 times)

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Offline Chris WilsonTopic starter

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Driving the gates of paralled FET's?
« on: December 25, 2016, 09:30:52 pm »



Firstly a very happy Christmas and a healthy and prosperous New Year to all, with great thanks for the great help members here have offered in 2016.

If you have a class D RF amplifier with two FET's in parallel each side would you use a separate gate driver resistor ans pull down resistor per device, or one driver resistor and pull down per pair, with the gates paralleled at the devices, like the sources and drains, and why please? If a single device had a 6R8 driver resistor and a 47k pull down on each gate, with each FET having it's own pair of resistors, would you change their value if feeding a pair of FET's, or even three FET's in parallel from one pair of resistors? Thanks.
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Offline T3sl4co1l

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Re: Driving the gates of paralled FET's?
« Reply #1 on: December 25, 2016, 10:57:58 pm »
The driver IC needs to be capable of driving the total gate load.

Use separate gate resistors.  This way, as different transistors begin to turn on (and hit the Miller plateau), they remain better matched than if they were hard wired together (gate to gate).

If the transistors are physically distant as well (a long row of them, perhaps), differences in ground voltage may become significant too.  In this case, it is better to use multiple driver ICs, each locally bypassed.  The signal source that fans out only needs to be logic-level (not gate-drive level, where the low impedance makes long distances prohibitive), and can be filtered to some extent for noise immunity.

Tim
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Offline Chris WilsonTopic starter

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Re: Driving the gates of paralled FET's?
« Reply #2 on: December 26, 2016, 01:22:09 am »
Hi Tim, thanks for finding time for a reply during the holidays! I have one particular FET that seems prone to dying at the very end of a WSPR transmission, and it's on a slightly longer gate resistor lead length. Scoping the two gates simultaneously shows the waveform superimposed, but I suspect clever techniques are needed to measure  that sort of then? I hopefully attach photos showing the way the one gate resistor lead is longer to go around a capacitor, do you reckon it might be enough to make a difference? Resistors are 6R8 with 27k to ground on each gate. The driver chips are single ones, I swapped them over and still the FET third from the left looking at the photos is the one that seems fragile. ALWAYS at the end of a WSPR cycle though, never at the beginning.... Cheers and all the best..
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Offline T3sl4co1l

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Re: Driving the gates of paralled FET's?
« Reply #3 on: December 26, 2016, 01:38:13 am »
Ew, terminal blocks.

End of transmission sounds more like drain voltage spiking because of supply inductance.

Tim
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Offline johansen

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Re: Driving the gates of paralled FET's?
« Reply #4 on: December 26, 2016, 06:24:38 am »
Ew, terminal blocks.

End of transmission sounds more like drain voltage spiking because of supply inductance.

Tim

i read this the first time as, "End of Discussion"

anyhow, Tim might be right. what frequency?
 

Offline Chris WilsonTopic starter

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Re: Driving the gates of paralled FET's?
« Reply #5 on: December 26, 2016, 08:31:06 am »
136kHz. Does it on a big linear bench supply at a modest 20V, or at full whack from the bench supply at 40V. It also does it on its normal low power supply of one ex computer server 50V supply, and on its normal high power of two server supplies in series to gib=ve 100V where it gives about a kW out.

 I rebuilt the amp as it was very Heath Robinson, and fitted the FET's on terminal blocks to make changing them a lot easier without dismantling. It seems a lot less reliable since... But this is just bench testing with long wires all over the place, before the rebuild it was in a steel cabinet with much shorter leads.

It does seem like it's something like back emf, in fact I have trouble with the over current sensor (Hall effect) triggering at end of transmission and I got as far as scoping the output of the comparator fed from the current sensing module, and saw this before a FET went pop again... The output goes low on over current and at 500uS per division to me it seems the pulse lasts about 4.7 m/seconds before the output is high again. I have yet to scope the actual current sensor output.

Should I try and scope the supply voltage?  Thanks.
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Offline Chris WilsonTopic starter

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Re: Driving the gates of paralled FET's?
« Reply #6 on: December 26, 2016, 12:37:36 pm »
This morning I repaired the blown FET and tried again, this time probing the drain pin of the FET that usually fails. WSPR has a tune mode that when closed never seems to blow a FET like when it ends a transmission. Now whwther the coding is different for end of the tune mode, compared to the end of a transmission I have no idea, but it's easier to test with tune as it can started and stopped at will, whilst a transmission, as those that know WSPR will be aware, only starts on even minutes and takes 2 minutes to complete. So, IMHO, this is a best case scenario. probe is set X10, so multiply the scale by 10. I had 23V input and it spikes to near 180V when I close the tune mode. I suspect this is what's killing the FETs? I am told they need to be rated 4X the highest input voltage they see. Heaven knows where the spike is at 100V. Am I on the right track, and how should I try and address this please?
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                 Chris Wilson.
 


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