Dynamic Electronic Load Project

[ogden]

I would say that for sake of circuit simplicity it may stay as it is because "overshoot problem" supposedly can be avoided by using power switch of the load - by powering it on only *after* connection to the DUT.

[ignilux]

I realize that this thread is now almost 6 years old, but I came across it again today and have spent some time playing with the excellent LTspice simulations provided by Jay_Diddy_B on the first page. I understand how the circuit as a whole and the individual blocks work, but I had a few questions for Jay and/or others.

First, I'm curious how the resistor values were determined on the grounded non-inverting inputs. Assuming that they're present for offset compensation, the method I'm familiar with says that the resistor should be equal to the parallel combination of the input and feedback resistances. However, the inverting summing amplifier, for example would require a different value depending on the position of the potentiometers, wouldn't it? How are things complicated by the presence of an active device in the feedback loop, as in the two error amplifiers driving the FETs?

Next, I'm wondering how the lead inductance damping network was chosen. The peak in the bode plot is at 200 kHz, and it looks like the cutoff frequency of the damping network is around 33 kHz. Was it simply a matter of picking something with a sufficiently low frequency as to roll the high frequency gain off before the peak, but high enough that the transient response didn't suffer?

Finally, I'm unsure how to interpret the results of some modifications that I made to the model. I've swapped the opamps and FETs, and adjusted the frequency compensation to get rid of some ringing on the rising edge of the load current waveform. However, despite having 80 degrees of phase margin and a gain margin of 20 dB, I'm still seeing 5% overshoot on the rising edges. The AC analysis would seem to indicate a rock-solid control loop, but the ringing gives me pause. What am I missing?

Thanks again to Jay_Diddy_B for being the in-house expert of spice, and for all the work he puts in to threads like these.

[Jay_Diddy_B]

Ignilux and the group,

Thank you for your kind words.

First, I'm curious how the resistor values were determined on the grounded non-inverting inputs. Assuming that they're present for offset compensation, the method I'm familiar with says that the resistor should be equal to the parallel combination of the input and feedback resistances. However, the inverting summing amplifier, for example would require a different value depending on the position of the potentiometers, wouldn't it? How are things complicated by the presence of an active device in the feedback loop, as in the two error amplifiers driving the FETs?

The general idea of having equal resistance on the non-inverting and inverting inputs is so that any bias currents in the op-amp input will not create an (additional) offset.

If you take the LM324, from the TI datasheet worst case input bias current is 500nA, over the full temperature range.
With 100k of feedback resistance this is converted to 50mV

Consider this model



If you run this model and plot the results:




The potentiometers can be converted to a voltage source and the Thevenin equivalent resistance. The Thevenin resistance will vary with the position of the potentiometer. The maximum resistance is when the wiper is in the middle. At this point the Thevenin resistance is half the value of the potentiometer 10k / 2 = 5k

Since the current is set by adjusting the potentiometer, the error introduced by the potentiometer doesn't matter.

Regards,

Jay_Diddy_B

[ignilux]

Aha! That's both a very clever, and surprisingly simple solution to the problem at hand. Why guess when you can measure?

[JaysonJT]

Hi,

In your constant current Mosfet model, may I know how you picked the 300p and 1000p capacitor values? Also, the gain of 3?

If Vds is 5V, I would have thought you'd pick the values on the red line as shown in the graph below:

[Jay_Diddy_B]

Hi,

In your constant current Mosfet model, may I know how you picked the 300p and 1000p capacitor values? Also, the gain of 3?

If Vds is 5V, I would have thought you'd pick the values on the red line as shown in the graph below:

JaysonJT,

Welcome to the forum!!

So, you want me to remember what I was thinking in June 2014? 



In this example I have increased the transconductance to 6.

Background

There are a tremendous number of load designs on the internet and almost as many questions on how stop a load from oscillating or my load oscillates when I increase the current.

This series of posts was 'engineered' to illustrate how to design a stable load and explain these effects.

When I used the MOSFET small-signal model with a transconductance and the two capacitors I was demonstrating that the ac performance was dominated be these parameters.

The real stability checks were done with the full MOSFET model.

Loop design

Control loops are normally designed with a phase margin greater than 45 degrees and again margin of at least 6dB.

There is a lot room for component tolerances with these margins.

Since the load could be used with any input from 0.5V to VDS rating of the MOSFET you should check stability at the worst case operating point.

In one of the messages I illustrated that if the loop is marginally, the control loop will oscillate if the load current is increased.

Regards,
Jay_Diddy_B

[zeo0d]

Hi Jay_Diddy_B,

i'm trying to design a pulsed load for different power LED configurations ( Current form 0-10A and Voltage from 0-200V), and i was going through the post and think that my problem was similar to what you designed.

But i will use DAC ( connected to opamp non-inverting input) for setting the current and voltage.

What i don't understand is: if i choose TPH5200FNH mosfet for my application how can i initially determine before simulation what OPAMP is most suited regarding to GWB, SR, output current capability, single or dual rail, settling time, VF opamp or CF opamp ?

i think i have to calculate the effective input capacitance of the mosfet from Qg total in order do determine what opapm do i need ? I'm not shore how to do that?

I want to pulse the load with max 1kHz ( most of the time is 200Hz) and the rise/fall time of mosfet turn on/off should be no more than 1us



Best Regards.

[Jay_Diddy_B]

Hi zeo0d,

Welcome to the forum.

This is an old thread that was started in September 2013, it just celebrated its 7th Birthday:





The thread is about designing a small to medium sized load for testing the transient response response of power supplies.

Your request for a high power circuit (0-10A, 0-200V) to test LED arrays is off-topic.

I suggest that you start a new topic. Indicate why you need the circuit and what you are hoping to measure with.

Regards,
Jay_Diddy_B

[Vovk_Z]

What i don't understand is: if i choose TPH5200FNH mosfet for my application how can i initially determine before simulation what OPAMP is most suited regarding to GWB, SR, output current capability, single or dual rail, settling time, VF opamp or CF opamp ?

I'm not sure about TPH5200FNH, it is possibly too weak even for very short duration of measurement. You have to carefully look at it's SOA, and don't work very close to the SOA border.
About opamp: I'l use some similar to was used in other fast electronic loads. There are one or two designs published in the internet. Or otherwise something like OP27/OPA189 may work (they are the fastest easy obtainable and still cheap precision opamps I know).
We usually use VF opamps here. CF opamps are typically faster but have lower accuracy (higher offset etc). You may use CF opamp if you really need much more speed then any VF opamp can give.

[blackdog]

Hi Jay_Diddy_B,

I was once again going through some topics that deal with "Electronic Loads"
As far as I can tell, your explanation is excellent!

As I myself use a faster Electronic Load(Jim Williams Design) for some tests, and you have also fitted your design with a faster opamp but that did not bring much faster edges.
Which I therefore think is too little current available to drive the Gate impedance fast enough.

Would it make sense to use e.g. an LT1010 as a buffer with a faster opamp to get a real jump in the edge speed?
The opamp used does not see a load when using the LT1010 and the LT1010 has a good drive capability for capacitive loads with its 7 Ohm output resistor.
Then to make it optimal, the gate resistance can be lowered a bit because the LT1010 already takes care of this for a large part.
A nice opamp with a lot of phase margin is the ADA4625 and this one also has inputs that includes V-
I am aware that these parts cost a bit more, but going out for dinner with your family costs a lot more and you usually forget about it after a few weeks :-)

Is it possible that you could test this once in LTSpice if you have the time?
My skills with LTSpice are not very good yet.
Building a test circuit now would be even faster for me :-)

I use this Active Load when I need fast edges.


Here is the above diagram in a box.
The Active Load is only used for speed testing and not for long time dissipating for much power.
I can mount a heatsink against the bottom as needed to dissipate some more.


For anyone working with fast or basically all Active Loads, twist your cabling between the source to be tested and the Active Load.
With the Jim Williams version as I showed above, every mm of wiring between the Active Load and the source is suspect if you want neat edges.
For anyone working with fast or basically all Active Loads, twist your cabling between the source to be tested and the Active Load.
With the Jim Williams version as I showed above, every mm of wiring between the Active Load and the source is suspect if you want neat flanks.

Thank and kind regads,
Bram