Hi,
We are working on a project to generate quadrature signals from DC to 800MHz for lock-in detection. Therefore, we were thinking about using flip-flops as divide-by-4 dividers to generate the quadrature signals for mixing.
The only flip-flops that we could find that work at such high clock rates are ECL D-flip-flops. Specifically, we bought NB7V52M from OnSemi and SY10EP51 from Microchip to try. We could not get NB7V52M to perform anything meaningful, but we managed to get SY10EP51 to change the output by changing the input on the D port manually on the breadboard.
However, when we connected the invert-Q output to a flip-flop's own D input, the output is stuck in voltage high all the time. To be more specific, the output is logic-high with the clock signal around 50 peak-to-peak mV, which I think is just the clock input coupled onto the output.
Hence, I wonder if it is even possible to use such flip-flops with feedback as frequency dividers or the ECL D-type flip flop require specific configurations to perform as a frequency divider?
All ECL outputs need pull-down resistors to function. You need to calculate the right resistor value to pull the right current from the output.
Typically, the Vee is -4.5 V for ECL 100K and -5.2 for 10K series chips. Logic levels are about -0.8 V for high, and -1.6 V for logic low.
Some other setups run the chips from Ground and +supply voltages, IBM ran their version on +1.25 V and -3V, so they could termiante to ground,
which required much heavier pull-down current.
Jon
All ECL outputs need pull-down resistors to function.
Since it's been a long time since I've used ECL or PECL, I just looked at the NB7V52M datasheet. This part has CML outputs which are designed to drive a 50 Ohm output resistor pulled up to to Vcc (Vcc is in the range of 1.7 to 2.6 V). The D and other inputs have a built-in termination resistor with several V
TERM pins that need to be connected to Vcc.
So the NB7V52M isn't a classic ECL part.
The SY10EP51 is truly ECL, and needs the external pulldown terminations.
How about the ON Semi MC100LVEL34. Perhaps a bit overkill, but...
All ECL outputs need pull-down resistors to function.
Since it's been a long time since I've used ECL or PECL, I just looked at the NB7V52M datasheet. This part has CML outputs which are designed to drive a 50 Ohm output resistor pulled up to to Vcc (Vcc is in the range of 1.7 to 2.6 V). The D and other inputs have a built-in termination resistor with several VTERM pins that need to be connected to Vcc.
To me the problem sounds like a termination problem as well. (P)ECL chips don't work without external termination resistors. The outputs are either open collector or open emitter outputs while keeping the transistors in their linear (non-saturated) operating point so the output voltage swing is not large. IOW: using (P)ECL with other logic requires some planning where it comes to the logic levels.
The NB7V52M should be relatively trivial to use as a divide by 2 counter. Connect Q to nD and nQ to D to make the output change polarity for each clock cycle. But it depends on the rest of the circuitry (input / output requirement) whether it is a good fit or not.
Instead of using flip flops, consider a clock distribution chip instead. These often have programmable dividers and phase shifters, and can be made to operate at frequencies of >1 GHz.
For example, the LTC6954-1 has three outputs, each with programmable delay and division ratio, and operates up to 1.6 GHz. Since the delay is digital (and an integer multiple of input clock cycles), the outputs if configured properly, will always be in quadrature for any input frequency. AD9508 is similar, with four outputs and a bit more flexibility in divider and phase shifter values.
All ECL outputs need pull-down resistors to function. You need to calculate the right resistor value to pull the right current from the output.
Typically, the Vee is -4.5 V for ECL 100K and -5.2 for 10K series chips. Logic levels are about -0.8 V for high, and -1.6 V for logic low.
Some other setups run the chips from Ground and +supply voltages, IBM ran their version on +1.25 V and -3V, so they could termiante to ground,
which required much heavier pull-down current.
Jon
Hi,
Thanks for all the suggestions. I went in the lab today and used a simple voltage divider of 2.2k & 3.3k with Vcc = 5V, Vee = GND for the output terminations.
After cranking the function generator's output amplitude to around 7.2V, I managed to get the SY10EP51 to function as a divide-by-2 dividers.
I guess the requirement of the high amplitude from the function generator is due to the fact that I'm feeding the CLK single-ended?(i.e. I left nClk open/floated and only connected CLK to the function generator's output)
Instead of using flip flops, consider a clock distribution chip instead. These often have programmable dividers and phase shifters, and can be made to operate at frequencies of >1 GHz.
For example, the LTC6954-1 has three outputs, each with programmable delay and division ratio, and operates up to 1.6 GHz. Since the delay is digital (and an integer multiple of input clock cycles), the outputs if configured properly, will always be in quadrature for any input frequency. AD9508 is similar, with four outputs and a bit more flexibility in divider and phase shifter values.
The chip seems decent enough. However, we are a bit inclined to the flip flop method since we can play with it more in the future. Using an IC would be easier but that also means the real juicy part kind of happens in a closed-box.
Thanks for mentioning the chip anyways.
Unused input should not be left open. They would more need a defined DC level and at least a capacitor to "ground".
Normally an ECL input should not need a large input signal, more like a rather small, like 100 mV to 1 V max.
ECL and CML type logic are basically a differential amplifier as "seen" from the input. ECL outputs requires a pull down load, whereas CML outputs requires a pull up load. Unloaded output CML is slightly faster than ECL since it has no emitter (or source for SCL) follower output.
A couple decades ago we designed ECL and CML with IBM SiGe BiCMOS processes (7hp, 8hp and 9hp), mostly for very high speed frequency dividers that operated up ~100GHz. If you are trying to push the limits of speed, then the special divider case, the "Resonate Frequency Divider" where the dividers resonate near the desired operating speed should be considered, resonance is usually achieved with inductive loading. Another type very high frequency divider is based upon a passive microwave mixer where the LO port is feed with the IF port after a passive Low Pass Filter, a simple analysis shows that the LO port frequency is Fi/2.
Anyway a really good source for many papers on these type frequency dividers is the IEEE Circuits & Systems and the Solid State Journals.
Edit: Forgot to mention one of the advantages of the bipolar CML or ECL over CMOS CML or SCL is the close-in phase noise. Bipolar transistors have a much lower 1/f noise corner than CMOS and this 1/f noise gets impressed upon the signal because of the non-linear nature of the divider and shows up as close-in phase noise. Recall we were able to achieve -170dBm/Hz at 1KHz offset phase noise with the superb SiGe bipolar transistors in IBM's SiGe BiCMOS processes. Close-in divider phase noise is a critical factor in achieving clean very high frequency synthesized signal sources.
Best,
Unused input should not be left open. They would more need a defined DC level and at least a capacitor to "ground".
That's not true for ECL. That has an explicit pulldown resistor on each input.
Some extra-fast chips even have on-chip 50R-terminations on-chip to Vtt.
CML delivers VCC via 50 Ohms as high level. That may be a drawback wrt
Noise/phase noise when VCC is not
really clean.
This is often seen on CML islands in boards that are CMOS otherwise.
From the SY10EP51 datasheet:
The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the /CLK input will be biased at VCC/2
(V
EE is ground in this case)
With a +5 V
CC the input common-mode voltage range appears to range from 2V to 5V, so it seems that one should be able to leave /CLK floating and drive CLK with a clock signal that is biased at V
CC/2. I don't know what ChasLu97 is doing with that 7.2V input -- this just seems wrong. I would expect the input to be fried.
Another important consideration in usage is not allowing the input bipolar device to enter Quasi-Saturation during the positive input excursion, and this includes any overshoot due to transmission line or inductive effects. Quasi-Saturation will slow the device down and if allowed to enter Full Saturation this really slows the device. This condition needs to be maintained over the supply and bias voltage variations and chip temperature.
We employed temperature & process compensated bias voltages and currents to keep the devices out of potential Quasi-Saturation, and even went so far as to not allow the OFF device in the differential configuration to be completely OFF wrt it's own collector current. This was to allow a small collector current to flow in the OFF device and keep the device Ft from essentially going to 0 when no collector current flows. Also the peak collector current wasn't allowed to venture into the area where the Kirk Effect would be engaged, so the device would swing collector currents from a small minimum usually less than 10% peak to near the Ft peak but not over, and maintain this under temperature, process and device variations. To maintain these conditions and seek the fastest possible performance required a somewhat complex biasing scheme.
One word of caution to those not familiar with high speed transistors, ICs, and bipolar design. The terms Quasi-Saturation and Full Saturation are terms that reflect the "Intrinsic Transistor", not the transistor or IC terminals, or even the device terminals at the physical transistor location on the chip. Various resistive elements exist between the "Intrinsic Transistor" and the device terminals, or IC terminals, even on the IC right at the active transistor area. These resistive elements cause a voltage drop as seen by the intrinsic transistor and even tho the device or IC terminal voltages may indicate a condition well away for any type of saturation, the Intrinsic Device may actually be saturated. You'll soon know this when the speed performance isn't what you expected
Best,