Energy saving 500mA pulse - Feedback Wanted

[BoomStick0117]

Hi All!

I'm currently working on a custom DC ground fault detector for a (personal) system I'm building.

For this device I'd like to have a "test" feature similar to other real devices on the market.
I wanted a actual current to flow through the hall effect sensor, but decided that 0.5A (12W through a resistor) would be a lot to deal with since the device is powered by 24VDC

I came up with the below:

A trickle charged capacitor that's attached to a BJT current source that's configured roughly for 0.5A.
providing a test signal into the opto-coupler would enable the circuit creating a roughly 0.5ms pulse of 500mA.
holding the test signal high would be okay since R301 limits the current that can be delivered.

The 2 hall effect sensors I'm looking at have a 90% detect time of 0.5us and 5us respectively so I'm hoping 500us should be way more than long enough to trigger the detector to latch.

I'm looking for any feedback on this design.

I can provided the rest of the GFD if anyone is interested as well!

Thanks,
David

[Terry Bites]

The time constant (Rdson+R304+ESR)*C301 sets the current pulse width assuming the capacitor can recharge fully between test pulses.
This time constant needs to be longer than the test pulse to operate correctly.


In your schematic the emitter of the opto has no path to ground. Q302 is off because there is no current flowing in R304 so the gate has no drive.
What amplitude is the test signal at the opto?
If its logic level then R305 is too high. You need a few mA at least. (The CTR of your opto is only 50%).
Optos are pretty slow, 10uS rise times are not untypical. That needs to be take into account in your sample window timing.

I've got alternative idea which overcomes some of the limitations the original circuit.
A TL431 provides more precise current limiting and clamps the gate to ~7V

[BoomStick0117]

Hi Terry!

Thanks for your input!

I completely forgot about TL431s as an option! I wanted to limit part count so I ruled out op amps other ICs 

The test pulse planned is a manual push button from a control cabinet push button, I should probably include a capacitor for "de-bouncing"...
Test signal amplitude would just be 24VDC or less, I wanted it to operate anywhere from 12V-36VDC but I plan on only using 24V.

Apologies on the Opto, I left whatever Eagle had as the PN compared to the spare Darlington Optos I had leftover from another project.
CTR curve shows hundreds of % between 0.5-1mA

Speed is not a huge concern for me, I imagine the Hall effect sensor will be perfectly fine acclimating to the slow current rise since the Td to 90% is a few us.
Looking back at the datasheet however, I'm noticing a very slow rise time at 60-300us..!
Would increasing the input current speed up the rise time?
LTV-81S: https://optoelectronics.liteon.com/upload/download/DS-70-96-0015/LTV-8X5%20series%201015.pdf

Hall Effects:
HO 6P   https://www.lem.com/sites/default/files/products_datasheets/ho-p-series-v4.pdf
LP(XX) 6 (or Similar) https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/692/lpsr_series.pdf

I may change the opto drive resistor to something closer to 10K.
That should give me slightly under 1mA at 12V and around 3.4mA at 36V. (while staying under 1/8W for 0805)

I forgot to add my capacitor value on there last time, which was 10uF, LT spice sims showed around 500us.
doubling the load resistor dissipation shouldn't require a 4x increase in capacitance... Right?

I'm trying to make a extremely flat and compact board due to my poor planning skills and purchasing a enclosure that was too tight of a fit making larger capacitors unattractive of an option.

I am slightly confused about your last comment; how might this circuit clamp the gate drive to under 7V?
Is this a factor of your R7 and R3 combined with a feature of the TL431?
My understanding would be R3 is used to provide guaranteed path to com for the Opto and R7 is just the current limiter/"pull up" for the Mosfet gate that the TL431 can manipulate to allow operation in the ohmic region correct?
Would it hurt to add a Zener clamp *just in case*?

I apologize for the questions, my electronics background is self taught with my main profession being industrial controls

I appreciate your time and value the feedback!

Thanks,
David

*I attached copies of the system drawings it's going in if anyone is interested!
**unsure how to effectively responding directly to posts, is quoting an acceptable medium?
***Changed PDFs to PNGs

The time constant (Rdson+R304+ESR)*C301 sets the current pulse width assuming the capacitor can recharge fully between test pulses.
This time constant needs to be longer than the test pulse to operate correctly.


In your schematic the emitter of the opto has no path to ground. Q302 is off because there is no current flowing in R304 so the gate has no drive.
What amplitude is the test signal at the opto?
If its logic level then R305 is too high. You need a few mA at least. (The CTR of your opto is only 50%).
Optos are pretty slow, 10uS rise times are not untypical. That needs to be take into account in your sample window timing.

I've got alternative idea which overcomes some of the limitations the original circuit.
A TL431 provides more precise current limiting and clamps the gate to ~7V
(Attachment Link)

[Terry Bites]

Feel free to ask, I cant guarantee a prompt response though.

Play with my simulation. Download the app.
Circuit file attached.

I saw the TL31 clamp at ~6v and didn't give it a second thought other than "that's handy".
The TL431 is spect to 36V but the mechanism behind this clamping voltage isn't clear.
The clamping voltage depends on the value of R7 and the TL431 operating current that flows in it.
So, yeah probably wishful thinking on my part. It might really work but a real gate Zener isn't a bad idea!
I thought about lame opto issues and had a rethink. The rise and fall times get worse with dwindling led current. I hate 'em.

https://github.com/NeelPatra/Micro-Cap-12-Archive

[PCB.Wiz]

Looking back at the datasheet however, I'm noticing a very slow rise time at 60-300us..!
Would increasing the input current speed up the rise time?
LTV-81S: https://optoelectronics.liteon.com/upload/download/DS-70-96-0015/LTV-8X5%20series%201015.pdf

That is a Darlington opto, you will not be using that.

I am slightly confused about your last comment; how might this circuit clamp the gate drive to under 7V?
...Would it hurt to add a Zener clamp *just in case*?

A low capacitance (low current) zener will not do much harm, and can be useful during testing, but the drive is of modest speed thru an opto, and the FET gate C and the '431 turn on gives only modest gate voltage overshoot.

Spice indicates a 431 + PC817A opto model, tuns on with a FET to 80% of regulation, in 9~13us ballparks.

Note there are many '431 out there, there are lower voltage ones at 1.25V and lower current ones.
The better vendors have current settling time curves like the ones below

[PCB.Wiz]

I would suggest a more modern lower voltage lower current VREF, but here is a spice run for a TL431A at 2.5V with a low Vth FET as that gives a general idea.
A 1.25V VREF voltage part and a low threshold MOSFET will turn on slightly faster as the slew rate of the opto + FET Vth has less voltage to cover.
For these models, (PC817A and TL431A)  an Opto output current of about 2.4mA current (and above) gave clean settling.
Higher drive again, can reduce the time to 80% - eg 12mA from a PC817D drops to 7.7µs, as the slew rate improves.

Addit : The rise shape is similar to the example in the TI data for Anode voltages regulating above VREF, with added delays for the Opto + Gate voltage offsets. (added below)

[BoomStick0117]

Feel free to ask, I cant guarantee a prompt response though.

I thought about lame opto issues and had a rethink. The rise and fall times get worse with dwindling led current. I hate 'em.

Hi Terry,

No Worries! I'm too busy with my day job to work on these projects often .

Thanks for the response. I'll likely still keep a gate Zener, I'm a huge fan of "insurance" components.
sounds like more opto input current means a faster response, I'll keep that in mind.

That is a Darlington opto, you will not be using that.

Spice indicates a 431 + PC817A opto model, tuns on with a FET to 80% of regulation, in 9~13us ballparks.

Note there are many '431 out there, there are lower voltage ones at 1.25V and lower current ones.
The better vendors have current settling time curves like the ones below

Hi PCB.Wiz,

Appreciate your response! I believe most of my TL431 or equivalent REF's are 1.25V left over from another project I was building.

What's with the hate towards Darlington optos? Just slow response?

Huh, I never even thought about what the start-up curve would look like... Interesting thing to remember for the future to consider on any device.
I'm not hugely concerned about the start-up time or clean edge of the pulse. even I imagine a 50us delay wouldn't matter too much if the pulse lasts 150us or longer...

For more context of the trigger/latch circuit:

The hall effect sensor outputs a 2.5V +-104mv/A signal. I send it through a negative feedback amp with the 2.5V ref to get 2.5V +- 1.04V/A (104mV * 10x gain)
This signal is sent to a pair of comparators at 2.5V +-trip point voltage.
LM393s respond pretty fast at a few (ns) Haven't nailed a good amp down yet, but my bench component (LM358) and any future choices will also have a pretty high slew rate. (LM358 has too high of an offset, a few mV can really crash my accuracy here.)

Attached circuit output will be inverted since the LM393s will be used in open collector.

CD4043 used as a one-shot latch, Capacitor in series with resistor, will create a short pulse to the "Set" pin of the CD4043 on each power cycle.
Detector output will pull "Reset" high, disabling the output (shutting off PV contactors)

Apologies for the dirty LT spice schematic and setup, I get a few minutes per day here and there to work on it

Out of curiosity, any real issue using a BJT as a dirty 0.6-0.7V "regulator" I'm just wondering if there's much advantage to the TL431 if current regulation can be ballpark?
delay times for a jellybean NPN such as the 2n3904 only have (ns) of response time.

Any interest from either of you in reviewing a 3.2V Battery cell regulator circuit? I've got another post looking for feedback.
Circuit/design. It'll end up in the same final system.

Thanks,
David

*I wanted to use OP07 but I believe it would not preform too well with single supply operation... 2V above -Vsup
Hence, it's existence in the LT spice schematic. Circuit tested with real parts on the bench with a LM358 and its works great. Need to find where my scope is in our moving boxes to get a better picture of how everything is operating...
** I wanted to reduce error from the Hall effect since its output is anchored by it's internal Vref. I thought I could reduce drift and error by incorporating it as the comparator refs. Feel free to tell me if that's a good idea or not!

[PCB.Wiz]

Out of curiosity, any real issue using a BJT as a dirty 0.6-0.7V "regulator" I'm just wondering if there's much advantage to the TL431 if current regulation can be ballpark?
delay times for a jellybean NPN such as the 2n3904 only have (ns) of response time.

Yes, you can use a BJT if you are ok with very relaxed specs.
The main issues are they have poor temperature stability, and need manual initial calibration.
One advantage they do have, is a lower voltage overhead.

The VREFs are much more temperature stable and you know the voltage usually to 1% or better, with 0.5% almost standard these days.
If you just want go/no-go pass/fail type testing, maybe a BJT is 'good enough'