Filter Synthesizer v1.0.0 - Released, Open-Source

[Analog Frontend Designer]

Source code https://github.com/vvmanin/FilterSynthesizer.git

Windows build https://github.com/vvmanin/FilterSynthesizer/releases/tag/v1.0.0

Hi everyone,

As a HW engineer focused on analog circuits, I usually faced with a lack of free filter design tools with extended capabilities like arbitrary notch placement etc.

Thats why I have decided to build own one. At first, it was just a several isolated python notebooks scripts. Then it was wrapped in a web UI for convenient use.

Under the hood:

- It uses a custom nested optimization loop (SciPy least_squares) to achieve the equiripple state, when passband or stopband modifications applied.

- Root extraction for non-standard cases is done using mpmath at 80 decimal places to prevent floating-point catastrophic cancellation on high-order polynomials.

- It handles asymmetric specifications, except an Elliptic Band-Reject asymmetric case.

- You can manually pin transmission zeros (notches) wherever you want, and the solver will re-optimize the passband (if possible) around them.

Filter Synthesizer

Disclaimer: This is a raw engineering beta. Solver is currently being served straight from a my home PC via Ngrok.
Current version provides as outputs Bode plot, pole-zero map, roots, transfer functions, and pole-zero-pairing.

Topology section coming soon, and while I work on it, your feedback would be valuable.
Throw some nasty specifications at it. If the solver fails to converge, or if the magnitude response does something mathematically illegal, let me know the exact specs so I can patch the application quickly.

[Analog Frontend Designer]

UPD
Now, program capabilities have been extended - it computes section component parameters and provides a resulting Bode plot, including Monte Carlo analysis.
Access via the same link: Filter Synthesizer

This demo has limited capabilities and covers only the lowpass filter type and VCVS (Sallen-Key) topologies.

Note that 1st-order sections are still not added, so the final realization is possible only for even-order filters, or if an absorbed 3rd-order section is used for odd orders.

How to use.
Left sidebar (expandable) - filter input parameters.

Tabs:
📊 Response Plots - bode plot of ideal response, according to synthesized transfer function;
🔢 Roots & Transfer Function - pole-zero map, transfer function formulas (including LaTeX string);
🧱 Biquad Pairing & Cascading - here pole paired with zeros (if exists), also manual interactive re-pairing is possible;
⚙️ Topology - real physics begins here, choosing section topology (now VCVS available only), solving, picking appropriate solution from table;
📉 Resulting Response & Schematic - tolerances definition and resulting bode plot, including Monte-Carlo analysis.

[Analog Frontend Designer]

UPD

I've been continuing development of the filter synthesis tool, with the latest update focusing on expanding the implementation solvers.
Filter Synthesizer

Support for the VCVS (Sallen–Key) family has been extended to cover every section type, including low-pass, low-pass notch, high-pass, high-pass notch, notch, and band-pass filters. The multiple-feedback family (Deliyannis–Friend and related topologies) now supports all of these except notch and band-pass sections.

Each filter section can be configured independently, with its own op-amp parameters and passive component constraints. The solver generates multiple valid implementations for every stage and ranks them according to their sensitivity. This allows you to compare alternatives, select the most practical implementation, and immediately inspect the resulting frequency response together with Monte Carlo analysis to evaluate the effects of component tolerances.

[Analog Frontend Designer]

Now is open-sourced under GPL-3.0 license.

Source code https://github.com/vvmanin/FilterSynthesizer.git

Windows build
old https://github.com/vvmanin/FilterSynthesizer/releases/tag/v1.0.0
new https://github.com/vvmanin/FilterSynthesizer/releases/tag/v1.0.1 - fixed “Engine Error: cannot load module more than once per process.”